pike.git/src/code/amd64.c:2ad55eb2ff181db012b7e5e2d62cc87f991bdf9e

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 /* * Machine code generator for AMD64. */ #include "operators.h" #include "constants.h" #include "object.h" #include "builtin_functions.h" #include "bignum.h" /* These come from linux include files. */ #ifdef REG_RBX #undef REG_RAX #undef REG_RBX #undef REG_RCX #undef REG_RDX #undef REG_RSP #undef REG_RBP #undef REG_RSI #undef REG_RDI #undef REG_R8 #undef REG_R9 #undef REG_R10 #undef REG_R11 #undef REG_R12 #undef REG_R13 #undef REG_R14 #undef REG_R15 #endif #define REG_RAX MISSING_P_ #define REG_RBX MISSING_P_ #define REG_RCX MISSING_P_ #define REG_RDX MISSING_P_ #define REG_RSP MISSING_P_ #define REG_RBP MISSING_P_ #define REG_RSI MISSING_P_ #define REG_RDI MISSING_P_ #define REG_R8 MISSING_P_ #define REG_R9 MISSING_P_ #define REG_R10 MISSING_P_ #define REG_R11 MISSING_P_ #define REG_R12 MISSING_P_ #define REG_R13 MISSING_P_ #define REG_R14 MISSING_P_ #define REG_R15 MISSING_P_ struct soff { int off; int type; int value; }; static struct soff SVAL(int i) { struct soff res; res.off = res.type = i*sizeof(struct svalue); res.value = res.type + 8; return res; } /* Register encodings */ enum amd64_reg {P_REG_RAX = 0, P_REG_RBX = 3, P_REG_RCX = 1, P_REG_RDX = 2, P_REG_RSP = 4, P_REG_RBP = 5, P_REG_RSI = 6, P_REG_RDI = 7, P_REG_R8 = 8, P_REG_R9 = 9, P_REG_R10 = 10, P_REG_R11 = 11, P_REG_R12 = 12, P_REG_R13 = 13, P_REG_R14 = 14, P_REG_R15 = 15, P_REG_INVALID = -1, P_REG_XMM0 = 0, P_REG_XMM1 = 1, P_REG_XMM2 = 2, P_REG_XMM3 = 3, P_REG_XMM4 = 4, P_REG_XMM5 = 5, P_REG_XMM6 = 6, P_REG_XMM7 = 7, P_REG_XMM8 = 8, P_REG_XMM9 = 9, P_REG_XMM10=10, P_REG_XMM11=11, P_REG_XMM12=12, P_REG_XMM13=13, P_REG_XMM14=14, P_REG_XMM15=15, }; #define PIKE_MARK_SP_REG P_REG_R12 #define PIKE_SP_REG P_REG_R13 #define PIKE_FP_REG P_REG_R14 #define Pike_interpreter_reg P_REG_R15 #ifdef __NT__ /* From http://software.intel.com/en-us/articles/introduction-to-x64-assembly/ * * Note: Space for the arguments needs to be allocated on the stack as well. */ #define ARG1_REG P_REG_RCX #define ARG2_REG P_REG_RDX #define ARG3_REG P_REG_R8 #define ARG4_REG P_REG_R9 #else /* From SysV ABI for AMD64 draft 0.99.5. */ #define ARG1_REG P_REG_RDI #define ARG2_REG P_REG_RSI #define ARG3_REG P_REG_RDX #define ARG4_REG P_REG_RCX #define ARG5_REG P_REG_R8 #define ARG6_REG P_REG_R9 #endif static enum amd64_reg sp_reg = -1, fp_reg = -1, mark_sp_reg = -1; static int dirty_regs = 0, ret_for_func = 0; ptrdiff_t amd64_prev_stored_pc = -1; /* PROG_PC at the last point Pike_fp->pc was updated. */ static int branch_check_threads_update_etc = 0; static int store_pc = 0; #define MAX_LABEL_USES 6 struct label { int n_label_uses; ptrdiff_t addr; ptrdiff_t offset[MAX_LABEL_USES]; }; static void label( struct label *l ) { int i; if (l->addr >= 0) Pike_fatal("Label reused.\n"); for( i=0; i<l->n_label_uses; i++ ) { int dist = PIKE_PC - (l->offset[i] + 1); if( dist > 0x7f || dist < -0x80 ) Pike_fatal("Branch %d too far\n", dist); Pike_compiler->new_program->program[l->offset[i]] = dist; } l->n_label_uses = 0; l->addr = PIKE_PC; } static void ib( char x ) { add_to_program( x ); } static void iw( short x ) { add_to_program( x ); add_to_program( x>>8 ); } static void id( int x ) { add_to_program( (x)&0xff ); add_to_program( (x>>8)&0xff ); add_to_program( (x>>16)&0xff ); add_to_program( (x>>24)&0xff ); } /* x86 opcodes */ #define opcode(X) ib(X) static void modrm( int mod, int r, int m ) { if (r < 0) Pike_fatal("Using an invalid register(1)!\n"); if (m < 0) Pike_fatal("Using an invalid register(2)!\n"); ib( ((mod<<6) | ((r&0x7)<<3) | (m&0x7)) ); } static void sib( int scale, int index, enum amd64_reg base ) { ib( (scale<<6) | ((index&0x7)<<3) | (base&0x7) ); } static void modrm_sib( int mod, int r, int m ) { modrm( mod, r, m ); if( (m&7) == P_REG_RSP) sib(0, P_REG_RSP, P_REG_RSP ); } static void rex( int w, enum amd64_reg r, int x, enum amd64_reg b ) { unsigned char res = 1<<6; /* bit 7, 5-4 == 0 */ if( w ) res |= 1<<3; if( r > 0x7 ) res |= 1<<2; if( x ) res |= 1<<1; if( b > 0x7 ) res |= 1<<0; if( res != (1<<6) ) add_to_program( res ); } static void offset_modrm_sib( int offset, int r, int m ) { /* OFFSET */ if( offset < -128 || offset > 127 ) { modrm_sib( 2, r, m ); id( offset ); } else if( offset || (m&7) == P_REG_RSP || (m&7) == P_REG_RBP ) { modrm_sib( 1, r, m ); ib( offset ); } else { modrm_sib( 0, r, m ); } } static void ret() { opcode(0xc3); } static void push(enum amd64_reg reg ) { if (reg < 0) Pike_fatal("Pushing invalid register.\n"); if (reg & 0x08) add_to_program(0x41); add_to_program(0x50 + (reg & 0x07)); } static void pop(enum amd64_reg reg ) { if (reg < 0) Pike_fatal("Popping invalid register.\n"); if (reg & 0x08) add_to_program(0x41); add_to_program(0x58 + (reg & 0x07)); } static void mov_reg_reg(enum amd64_reg from_reg, enum amd64_reg to_reg ) { rex( 1, from_reg, 0, to_reg ); opcode( 0x89 ); modrm( 3, from_reg, to_reg ); } static void mov_reg32_reg(enum amd64_reg from_reg, enum amd64_reg to_reg ) { rex( 0, from_reg, 0, to_reg ); opcode( 0x89 ); modrm( 3, from_reg, to_reg ); } #define PUSH_INT(X) ins_int((INT32)(X), (void (*)(char))add_to_program) static void low_mov_mem_reg(enum amd64_reg from_reg, ptrdiff_t offset, enum amd64_reg to_reg) { opcode( 0x8b ); offset_modrm_sib(offset, to_reg, from_reg ); } static void mov_mem_reg( enum amd64_reg from_reg, ptrdiff_t offset, enum amd64_reg to_reg ) { rex( 1, to_reg, 0, from_reg ); low_mov_mem_reg( from_reg, offset, to_reg ); } static void xor_reg_reg( enum amd64_reg reg1, enum amd64_reg reg2 ) { rex(1,reg1,0,reg2); opcode( 0x31 ); modrm(3,reg1,reg2); } static void and_reg_reg( enum amd64_reg reg1, enum amd64_reg reg2 ) { rex(1,reg1,0,reg2); opcode( 0x23 ); modrm(3,reg1,reg2); } static void or_reg_reg( enum amd64_reg reg1, enum amd64_reg reg2 ) { rex(1,reg1,0,reg2); opcode( 0x09 ); modrm(3,reg1,reg2); } static void or_reg_imm( enum amd64_reg reg, INT_TYPE imm32 ) { rex( 1, 0, 0, reg ); if( imm32 < -0x80 || imm32 > 0x7f ) { if( reg == P_REG_RAX ) { opcode( 0xd ); /* OR rax,imm32 */ id( imm32 ); } else { opcode( 0x81 ); /* OR REG,imm32 */ modrm( 3, 1, reg); id( imm32 ); } } else { add_to_program(0x83); /* OR REG,imm8 */ modrm( 3, 1, reg ); ib( imm32 ); } } static void and_reg_imm( enum amd64_reg reg, INT_TYPE imm32 ) { rex( 1, 0, 0, reg ); if( imm32 < -0x80 || imm32 > 0x7f ) { if( reg == P_REG_RAX ) { opcode( 0x25 ); /* AND rax,imm32 */ id( imm32 ); } else { opcode( 0x81 ); /* AND REG,imm32 */ modrm( 3,4, reg); id( imm32 ); } } else { add_to_program(0x83); /* AND REG,imm8 */ modrm( 3, 4, reg ); ib( imm32 ); } } static void and_reg32_imm( enum amd64_reg reg, int imm32 ) { rex( 0, 0, 0, reg ); if( imm32 < -0x80 || imm32 > 0x7f ) { if( reg == P_REG_RAX ) { opcode( 0x25 ); /* AND rax,imm32 */ id( imm32 ); } else { opcode( 0x81 ); /* AND REG,imm32 */ modrm( 3,4, reg); id( imm32 ); } } else { add_to_program(0x83); /* AND REG,imm8 */ modrm( 3, 4, reg ); ib( imm32 ); } } static void mov_mem32_reg( enum amd64_reg from_reg, ptrdiff_t offset, enum amd64_reg to_reg ) { rex( 0, to_reg, 0, from_reg ); low_mov_mem_reg( from_reg, offset, to_reg ); } static void mov_mem16_reg( enum amd64_reg from_reg, ptrdiff_t offset, enum amd64_reg to_reg ) { #if 0 mov_mem32_reg( from_reg, offset, to_reg ); and_reg_imm(to_reg, 0xffff); #else rex( 1,to_reg,0,from_reg ); /* movzx r/m16 -> r32. This automatically zero-extends the upper 32-bit */ opcode( 0xf ); opcode( 0xb7 ); offset_modrm_sib(offset, to_reg, from_reg ); #endif } static void mov_mem8_reg( enum amd64_reg from_reg, ptrdiff_t offset, enum amd64_reg to_reg ) { #if 0 mov_mem32_reg( from_reg, offset, to_reg ); and_reg_imm(to_reg, 0xff); #else rex( 0,to_reg,0,from_reg ); /* movzx r/m8 -> r32. This automatically zero-extends the upper 32-bit */ opcode( 0xf ); opcode( 0xb6 ); offset_modrm_sib(offset, to_reg, from_reg ); #endif } static void add_reg_imm( enum amd64_reg src, int imm32); static void shl_reg_imm( enum amd64_reg from_reg, int shift ) { rex( 1, from_reg, 0, 0 ); if( shift == 1 ) { opcode( 0xd1 ); /* SAL */ modrm( 3, 4, from_reg ); } else { opcode( 0xc1 ); modrm( 3, 4, from_reg ); ib( shift ); } } static void shl_reg_reg( enum amd64_reg reg, enum amd64_reg sreg) { if( sreg != P_REG_RCX ) Pike_fatal("Not supported\n"); rex( 1, 0, 0, reg ); opcode( 0xd3 ); modrm( 3, 4, reg ); } static void shl_reg32_reg( enum amd64_reg reg, enum amd64_reg sreg) { if( sreg != P_REG_RCX ) Pike_fatal("Not supported\n"); rex( 0, 0, 0, reg ); opcode( 0xd3 ); modrm( 3, 4, reg ); } static void shr_mem_reg( enum amd64_reg reg, int off, enum amd64_reg sreg) { if( sreg != P_REG_RCX ) Pike_fatal("Not supported\n"); rex( 1, 0, 0, reg ); opcode( 0xd3 ); /* SAR r/m64,CL */ offset_modrm_sib(off, 7, reg ); /* modrm( 3, 7, reg ); */ } static void shr_reg_reg( enum amd64_reg reg, enum amd64_reg reg_rcx ) { if( reg_rcx != P_REG_RCX ) Pike_fatal("Not supported\n"); rex( 1, 0, 0, reg ); opcode( 0xd3 ); /* SAR r/m64,CL */ modrm( 3, 7, reg ); } static void shr_reg_imm( enum amd64_reg from_reg, int shift ) { rex( 1, from_reg, 0, 0 ); if( shift == 1 ) { opcode( 0xd1 ); /* SAR */ modrm( 3, 7, from_reg ); } else { opcode( 0xc1 ); modrm( 3, 7, from_reg ); ib( shift ); } } static void clear_reg( enum amd64_reg reg ) { xor_reg_reg( reg, reg ); } #if 0 static void neg_reg( enum amd64_reg reg ) { rex(1,0,0,reg); opcode(0xf7); modrm(3,3,reg); } #endif static void mov_imm_reg( long imm, enum amd64_reg reg ) { if( !imm ) { clear_reg(reg); return; } if( (imm > 0x7fffffffLL) || (imm < -0x80000000LL) ) { rex(1,0,0,reg); opcode(0xb8 | (reg&0x7)); /* mov imm64 -> reg64 */ id( (imm & 0xffffffffLL) ); id( ((imm >> 32)&0xffffffffLL) ); } else if( imm > 0 ) { rex(0,0,0,reg); opcode( 0xc7 ); /* mov imm32 -> reg/m 32, SE*/ modrm( 3,0,reg ); id( (int)imm ); } else { rex(1,0,0,reg); opcode( 0xc7 ); /* mov imm32 -> reg/m 64, SE*/ modrm( 3,0,reg ); id( (int)imm ); } } /* static void mov_ptr_reg( void *x, enum amd64_reg reg ) */ /* { */ /* mov_imm_reg( (long)x, reg ); */ /* } */ static void mov_mem128_reg( enum amd64_reg from_reg, int offset, enum amd64_reg to_reg ) { if( from_reg > 7 ) Pike_fatal("Not supported\n"); rex(0,to_reg,0,from_reg); opcode( 0x66 ); opcode( 0x0f ); opcode( 0x6f ); /* MOVDQA xmm,m128 */ offset_modrm_sib( offset, to_reg, from_reg ); } static void mov_reg_mem128( enum amd64_reg from_reg, enum amd64_reg to_reg, int offset ) { if( from_reg > 7 ) Pike_fatal("Not supported\n"); rex(0,from_reg,0,to_reg); opcode( 0x66 ); opcode( 0x0f ); opcode( 0x7f ); /* MOVDQA m128,xmm */ offset_modrm_sib( offset, from_reg, to_reg ); } static void low_set_if_cond(unsigned char subop, enum amd64_reg reg) { rex( 0, 0, 0, reg ); opcode( 0xf ); opcode( subop ); modrm( 3, 0, reg ); } static void set_if_lt(enum amd64_reg reg) { low_set_if_cond( 0x9c, reg ); } static void set_if_lte(enum amd64_reg reg) { low_set_if_cond( 0x9e, reg ); } static void set_if_gt(enum amd64_reg reg) { low_set_if_cond( 0x9f, reg ); } static void set_if_gte(enum amd64_reg reg) { low_set_if_cond( 0x9d, reg ); } static void set_if_eq(enum amd64_reg reg) { low_set_if_cond( 0x94, reg ); } static void set_if_neq(enum amd64_reg reg) { low_set_if_cond( 0x95, reg ); } #if 0 static void low_mov_if_cond_reg(unsigned char subop, enum amd64_reg to_reg, enum amd64_reg from_reg ) { rex(0, from_reg, 0, to_reg ); opcode( 0xf ); opcode( subop ); modrm_sib( 3, from_reg, to_reg ); } static void mov_if_lte_reg( enum amd64_reg from_reg, enum amd64_reg to_reg ) { low_mov_if_cond_reg( 0x4e, from_reg, to_reg); } static void mov_if_gte_reg( enum amd64_reg from_reg, enum amd64_reg to_reg ) { low_mov_if_cond_reg( 0x4d, from_reg, to_reg ); } static void mov_if_lt_reg( enum amd64_reg from_reg, enum amd64_reg to_reg ) { low_mov_if_cond_reg( 0x4c, from_reg, to_reg ); } static void mov_if_gt_reg( enum amd64_reg from_reg, enum amd64_reg to_reg ) { low_mov_if_cond_reg( 0x4f, from_reg, to_reg ); } static void mov_if_neq_reg( enum amd64_reg from_reg, enum amd64_reg to_reg ) { low_mov_if_cond_reg( 0x45, from_reg, to_reg ); } static void mov_if_eq_reg( enum amd64_reg from_reg, enum amd64_reg to_reg ) { low_mov_if_cond_reg( 0x44, from_reg, to_reg ); } #endif static void low_mov_reg_mem(enum amd64_reg from_reg, enum amd64_reg to_reg, ptrdiff_t offset ) { opcode( 0x89 ); offset_modrm_sib( offset, from_reg, to_reg ); } static void mov_reg_mem( enum amd64_reg from_reg, enum amd64_reg to_reg, ptrdiff_t offset ) { rex(1, from_reg, 0, to_reg ); low_mov_reg_mem( from_reg, to_reg, offset ); } static void mov_reg_mem32( enum amd64_reg from_reg, enum amd64_reg to_reg, ptrdiff_t offset ) { rex(0, from_reg, 0, to_reg ); low_mov_reg_mem( from_reg, to_reg, offset ); } #if 0 static void mov_reg_mem16( enum amd64_reg from_reg, enum amd64_reg to_reg, ptrdiff_t offset ) { opcode( 0x66 ); rex(0, from_reg, 0, to_reg ); low_mov_reg_mem( from_reg, to_reg, offset ); } #endif static void mov_imm_mem16( short imm, enum amd64_reg to_reg, ptrdiff_t offset ) { opcode( 0x66 ); /* switch 32/16 */ /* basically copy of mov_imm_mem32 */ rex( 0, 0, 0, to_reg ); opcode( 0xc7 ); /* now: mov imm16 -> r/m16 (sign extend)*/ /* This does not work for rg&7 == 4 or 5. */ offset_modrm_sib( offset, 0, to_reg ); iw( imm ); } static void mov_imm_mem( long imm, enum amd64_reg to_reg, ptrdiff_t offset ) { if( imm >= -0x80000000LL && imm <= 0x7fffffffLL ) { rex( 1, 0, 0, to_reg ); opcode( 0xc7 ); /* mov imm32 -> r/m64 (sign extend)*/ offset_modrm_sib( offset, 0, to_reg ); id( imm ); } else { if( to_reg == P_REG_RAX ) Pike_fatal( "Clobbered TMP P_REG_RAX reg\n"); mov_imm_reg( imm, P_REG_RAX ); mov_reg_mem( P_REG_RAX, to_reg, offset ); } } static void mov_imm_mem32( int imm, enum amd64_reg to_reg, ptrdiff_t offset ) { rex( 0, 0, 0, to_reg ); opcode( 0xc7 ); /* mov imm32 -> r/m32 (sign extend)*/ /* This does not work for rg&7 == 4 or 5. */ offset_modrm_sib( offset, 0, to_reg ); id( imm ); } static void sub_reg_imm( enum amd64_reg reg, int imm32 ); static void neg_mem( enum amd64_reg reg, int off ) { rex( 1, 0, 0, reg ); opcode(0xf7); offset_modrm_sib( off, 3, reg ); } static void not_mem( enum amd64_reg reg, int off ) { rex( 1, 0, 0, reg ); opcode(0xf7); offset_modrm_sib( off, 2, reg ); } static void add_reg_imm( enum amd64_reg reg, int imm32 ) { if( !imm32 ) return; if( imm32 < 0 ) { /* This makes the disassembly easier to read. */ sub_reg_imm( reg, -imm32 ); return; } rex( 1, 0, 0, reg ); if( imm32 < -0x80 || imm32 > 0x7f ) { if( reg == P_REG_RAX ) { opcode( 0x05 ); /* ADD rax,imm32 */ id( imm32 ); } else { opcode( 0x81 ); /* ADD REG,imm32 */ modrm( 3, 0, reg); id( imm32 ); } } else { add_to_program(0x83); /* ADD REG,imm8 */ modrm( 3, 0, reg ); ib( imm32 ); } } static void low_add_mem_imm(int w, enum amd64_reg reg, int offset, int imm32 ) { int r2 = imm32 == -1 ? 1 : 0; int large = 0; if( !imm32 ) return; rex( w, 0, 0, reg ); if( r2 ) imm32 = -imm32; if( imm32 == 1 ) opcode( 0xff ); /* INCL(DECL) r/m32 */ else if( imm32 >= -128 && imm32 < 128 ) opcode( 0x83 ); /* ADD imm8,r/m32 */ else { opcode( 0x81 ); /* ADD imm32,r/m32 */ large = 1; } offset_modrm_sib( offset, r2, reg ); if( imm32 != 1 ) { if( large ) id( imm32 ); else ib( imm32 ); } } static void add_mem32_imm( enum amd64_reg reg, int offset, int imm32 ) { low_add_mem_imm( 0, reg, offset, imm32 ); } static void add_mem_imm( enum amd64_reg reg, int offset, int imm32 ) { low_add_mem_imm( 1, reg, offset, imm32 ); } #ifndef USE_VALGRIND static void add_mem8_imm( enum amd64_reg reg, int offset, int imm32 ) { int r2 = imm32 == -1 ? 1 : 0; if( !imm32 ) return; rex( 0, 0, 0, reg ); if( imm32 == 1 || imm32 == -1 ) opcode( 0xfe ); /* INCL r/m8 */ else if( imm32 >= -128 && imm32 < 128 ) opcode( 0x80 ); /* ADD imm8,r/m32 */ else Pike_fatal("Not sensible"); offset_modrm_sib( offset, r2, reg ); if( imm32 != 1 && !r2 ) { ib( imm32 ); } } #endif static void sub_reg_imm( enum amd64_reg reg, int imm32 ) { if( !imm32 ) return; if( imm32 < 0 ) /* This makes the disassembly easier to read. */ return add_reg_imm( reg, -imm32 ); rex( 1, 0, 0, reg ); if( imm32 < -0x80 || imm32 > 0x7f ) { if( reg == P_REG_RAX ) { opcode( 0x2d ); /* SUB rax,imm32 */ id( imm32 ); } else { opcode( 0x81 ); /* SUB REG,imm32 */ modrm( 3, 5, reg); id( imm32 ); } } else { opcode(0x83); /* SUB REG,imm8 */ modrm( 3, 5, reg ); ib( imm32 ); } } static void test_reg_reg( enum amd64_reg reg1, enum amd64_reg reg2 ) { rex(1,reg1,0,reg2); opcode(0x85); modrm(3, reg1, reg2 ); } static void test_reg32_reg( enum amd64_reg reg1, enum amd64_reg reg2 ) { rex(0,reg1,0,reg2); opcode(0x85); modrm(3, reg1, reg2 ); } static void test_reg( enum amd64_reg reg1 ) { test_reg_reg( reg1, reg1 ); } static void test_reg32( enum amd64_reg reg1 ) { test_reg32_reg( reg1, reg1 ); } static void cmp_reg_imm( enum amd64_reg reg, int imm32 ) { if(!imm32) { test_reg( reg ); return; } rex(1, 0, 0, reg); if( imm32 > 0x7f || imm32 < -0x80 ) { if( reg == P_REG_RAX ) { opcode( 0x3d ); id( imm32 ); } else { opcode( 0x81 ); modrm(3,7,reg); id( imm32 ); } } else { opcode( 0x83 ); modrm( 3,7,reg); ib( imm32 ); } } static void cmp_reg32_imm( enum amd64_reg reg, int imm32 ) { if(!imm32) { test_reg32( reg ); return; } rex(0, 0, 0, reg); if( imm32 > 0x7f || imm32 < -0x80 ) { if( reg == P_REG_RAX ) { opcode( 0x3d ); id( imm32 ); } else { opcode( 0x81 ); modrm(3,7,reg); id( imm32 ); } } else { opcode( 0x83 ); modrm( 3,7,reg); ib( imm32 ); } } static void cmp_reg_reg( enum amd64_reg reg1, enum amd64_reg reg2 ) { rex(1, reg2, 0, reg1); opcode( 0x39 ); modrm( 3, reg2, reg1 ); } static int jmp_rel_imm32( int addr ) { int rel = addr - (PIKE_PC + 5); // counts from the next instruction int res; opcode( 0xe9 ); res = PIKE_PC; id( rel ); return res; } static void jmp_rel_imm( int addr ) { int rel = addr - (PIKE_PC + 2); // counts from the next instruction if(rel >= -0x80 && rel <= 0x7f ) { opcode( 0xeb ); ib( rel ); return; } jmp_rel_imm32( addr ); } static void call_rel_imm32( int addr ) { int rel = addr - (PIKE_PC + 5); // counts from the next instruction opcode( 0xe8 ); id( rel ); sp_reg = -1; return; } static void jmp_reg( enum amd64_reg reg ) { rex(0,reg,0,0); opcode( 0xff ); modrm( 3, 4, reg ); } static void call_reg( enum amd64_reg reg ) { rex(0,reg,0,0); opcode( 0xff ); modrm( 3, 2, reg ); } static void call_imm( void *ptr ) { size_t addr = (size_t)ptr; if( (addr & ~0x7fffffffLL) && !(addr & ~0x3fffffff8LL) ) { mov_imm_reg( addr>>3, P_REG_RAX); shl_reg_imm( P_REG_RAX, 3 ); } else { mov_imm_reg(addr, P_REG_RAX ); } call_reg( P_REG_RAX ); } /* reg += reg2 */ static void add_reg_reg( enum amd64_reg reg, enum amd64_reg reg2 ) { rex(1,reg2,0,reg); opcode( 0x1 ); modrm( 3, reg2, reg ); } /* reg *= reg2 res in rdx:rax */ static void mul_rax_reg_reg128( enum amd64_reg reg ) { /* 64b * 64b -> 128b This would actually not need an overflow check. instead, push high if not zero, push low, genreate gmp. but... Well. */ rex(1,0,0,reg); /* imul r/m64 */ opcode( 0xf7 ); modrm( 3,5,reg ); } /* reg *= reg2 */ static void mul_reg_reg( enum amd64_reg reg, enum amd64_reg reg2 ) { rex(1,reg,0,reg2); opcode( 0xf ); opcode( 0xaf ); modrm( 3, reg, reg2 ); } /* reg /= reg2 */ static void div_reg_reg( enum amd64_reg reg, enum amd64_reg reg2 ) { if( reg != P_REG_RAX ) Pike_error("Not supported, reg1 must be RAX\n"); if( reg2 == P_REG_RDX ) Pike_error("Clobbers RAX+RDX\n"); rex(1,0,0,0); opcode(0x99); /* *cqo: *sign extend 64bit rax -> 128bit in rdx:rax */ rex(1,0,0,reg2); opcode( 0xf7 ); modrm( 3, 7, reg2 ); /* idiv, ax = dx:ax / reg2 dx = dx:ax % reg2 */ } /* reg += reg2 */ static void add_reg32_reg32( enum amd64_reg reg, enum amd64_reg reg2 ) { rex(0,reg2,0,reg); opcode( 0x1 ); modrm( 3, reg2, reg ); } /* reg -= reg2 */ static void sub_reg_reg( enum amd64_reg reg, enum amd64_reg reg2 ) { rex(1,reg2,0,reg); opcode( 0x29 ); modrm( 3, reg2, reg ); } /* dst += *(src+off) */ static void add_reg_mem( enum amd64_reg dst, enum amd64_reg src, long off ) { rex(1,dst,0,src); opcode( 0x3 ); offset_modrm_sib( off, dst, src ); } /* dst -= *(src+off) */ static void sub_reg_mem( enum amd64_reg dst, enum amd64_reg src, long off ) { rex(1,dst,0,src); opcode( 0x2b ); offset_modrm_sib( off, dst, src ); } /* dst = src + imm32 (LEA, does not set flags!) */ static void add_reg_imm_reg( enum amd64_reg src, long imm32, enum amd64_reg dst ) { if( imm32 > 0x7fffffffLL || imm32 <-0x80000000LL) Pike_fatal("LEA [reg+imm] > 32bit Not supported\n"); if( src == dst ) { if( !imm32 ) return; add_reg_imm( src, imm32 ); } else { if( !imm32 ) { mov_reg_reg( src, dst ); return; } rex(1,dst,0,src); opcode( 0x8d ); /* LEA r64,m */ offset_modrm_sib( imm32, dst, src ); } } /* load code adress + imm to reg, always 32bit offset */ static void mov_rip_imm_reg( int imm, enum amd64_reg reg ) { imm -= 7; /* The size of this instruction. */ rex( 1, reg, 0, 0 ); opcode( 0x8d ); /* LEA */ modrm( 0, reg, 5 ); id( imm ); } static void add_imm_mem( int imm32, enum amd64_reg reg, int offset ) { int r2 = (imm32 == -1) ? 1 : 0; int large = 0; /* OPCODE */ rex( 1, 0, 0, reg ); if( imm32 == 1 || imm32 == -1 ) opcode( 0xff ); /* INCL(decl) r/m32 */ else if( -128 <= imm32 && 128 > imm32 ) opcode( 0x83 ); /* ADD imm8,r/m32 */ else { opcode( 0x81 ); /* ADD imm32,r/m32 */ large = 1; } offset_modrm_sib( offset, r2, reg ); /* VALUE */ if( imm32 != 1 && !r2 ) { if( large ) id( imm32 ); else ib( imm32 ); } } static void jump_rel8( struct label *res, unsigned char op ) { opcode( op ); if (res->addr >= 0) { ib(res->addr - (PIKE_PC+1)); return; } if( res->n_label_uses >= MAX_LABEL_USES ) Pike_fatal( "Label used too many times\n" ); res->offset[res->n_label_uses] = PIKE_PC; res->n_label_uses++; ib(0); } static int jnz_imm_rel32( int rel ) { int res; opcode( 0xf ); opcode( 0x85 ); res = PIKE_PC; id( rel ); return res; } static int jz_imm_rel32( int rel ) { int res; opcode( 0xf ); opcode( 0x84 ); res = PIKE_PC; id( rel ); return res; } #define jne(X) jnz(X) #define je(X) jz(X) static void jmp( struct label *l ) { return jump_rel8( l, 0xeb ); } static void jo( struct label *l ) { return jump_rel8( l, 0x70 ); } static void jno( struct label *l ) { return jump_rel8( l, 0x71 ); } static void jz( struct label *l ) { return jump_rel8( l, 0x74 ); } static void jnz( struct label *l ) { return jump_rel8( l, 0x75 ); } static void js( struct label *l ) { return jump_rel8( l, 0x78 ); } static void jl( struct label *l ) { return jump_rel8( l, 0x7c ); } static void jge( struct label *l ) { return jump_rel8( l, 0x7d ); } static void jle( struct label *l ) { return jump_rel8( l, 0x7e ); } #if 0 static void jc( struct label *l ) { return jump_rel8( l, 0x72 ); } static void jnc( struct label *l ) { return jump_rel8( l, 0x73 ); } static void jg( struct label *l ) { return jump_rel8( l, 0x7f ); } #endif #define LABELS() struct label label_A, label_B, label_C, label_D, label_E;label_A.addr = -1;label_A.n_label_uses = 0;label_B.addr = -1;label_B.n_label_uses = 0;label_C.addr = -1;label_C.n_label_uses = 0;label_D.addr = -1;label_D.n_label_uses = 0;label_E.addr=-1;label_E.n_label_uses=0; #define LABEL_A label(&label_A) #define LABEL_B label(&label_B) #define LABEL_C label(&label_C) #define LABEL_D label(&label_D) #define LABEL_E label(&label_E) static void amd64_ins_branch_check_threads_etc(int code_only); static int func_start = 0; /* Called at the start of a function. */ void amd64_start_function(int store_lines ) { store_pc = store_lines; branch_check_threads_update_etc = 0; /* * store_lines is true for any non-constant evaluation function * In reality we should only do this if we are going to be using * check_threads_etc (ie, if we have a loop). * * It does not really waste all that much space in the code, though. * * We could really do this one time per program instead of once per * function. * * But it is very hard to know when a new program starts, and * PIKE_PC is not reliable as a marker since constant evaluations * are also done using this code. So for now, waste ~20 bytes per * function in the program code. */ if( store_lines ) amd64_ins_branch_check_threads_etc(1); func_start = PIKE_PC; } /* Called when the current function is done */ void amd64_end_function(int UNUSED(no_pc)) { branch_check_threads_update_etc = 0; } /* Machine code entry prologue. * * On entry: * RDI: Pike_interpreter (ARG1_REG) * * During interpreting: * R15: Pike_interpreter */ void amd64_ins_entry(void) { size_t orig_ppc = PIKE_PC; /* Push all registers that the ABI requires to be preserved. */ push(P_REG_RBP); mov_reg_reg(P_REG_RSP, P_REG_RBP); push(P_REG_R15); push(P_REG_R14); push(P_REG_R13); push(P_REG_R12); push(P_REG_RBX); sub_reg_imm(P_REG_RSP, 8); /* Align on 16 bytes. */ mov_reg_reg(ARG1_REG, Pike_interpreter_reg); amd64_flush_code_generator_state(); if( PIKE_PC - orig_ppc != ENTRY_PROLOGUE_SIZE ) /* sanity check */ Pike_fatal("ENTRY_PROLOGUE_SIZE incorrectly set, should be 0x%x\n", PIKE_PC-orig_ppc ); } void amd64_flush_code_generator_state(void) { amd64_prev_stored_pc = -1; ret_for_func = 0; fp_reg = -1; sp_reg = -1; mark_sp_reg = -1; dirty_regs = 0; } static void flush_dirty_regs(void) { /* NB: PIKE_FP_REG is currently never dirty. */ if (dirty_regs & (1 << PIKE_SP_REG)) { mov_reg_mem(PIKE_SP_REG, Pike_interpreter_reg, OFFSETOF(Pike_interpreter_struct, stack_pointer)); dirty_regs &= ~(1 << PIKE_SP_REG); } if (dirty_regs & (1 << PIKE_MARK_SP_REG)) { mov_reg_mem(PIKE_MARK_SP_REG, Pike_interpreter_reg, OFFSETOF(Pike_interpreter_struct, mark_stack_pointer)); dirty_regs &= ~(1 << PIKE_MARK_SP_REG); } } /* NB: We load Pike_fp et al into registers that * are persistent across function calls. */ static void amd64_load_fp_reg(void) { if (fp_reg < 0) { mov_mem_reg(Pike_interpreter_reg, OFFSETOF(Pike_interpreter_struct, frame_pointer), PIKE_FP_REG); fp_reg = PIKE_FP_REG; } } static void amd64_load_sp_reg(void) { if (sp_reg < 0) { mov_mem_reg(Pike_interpreter_reg, OFFSETOF(Pike_interpreter_struct, stack_pointer), PIKE_SP_REG); sp_reg = PIKE_SP_REG; } } static void amd64_load_mark_sp_reg(void) { if (mark_sp_reg < 0) { mov_mem_reg(Pike_interpreter_reg, OFFSETOF(Pike_interpreter_struct, mark_stack_pointer), PIKE_MARK_SP_REG); mark_sp_reg = PIKE_MARK_SP_REG; } } static void mov_sval_type(enum amd64_reg src, enum amd64_reg dst ) { mov_mem8_reg( src, SVAL(0).type, dst); /* and_reg32_imm( dst, 0x1f );*/ } #if 0 static void svalue_is_referenced(enum amd64_reg in, struct label *not ) { /* bit 4 set, and no higher bit set (all with 8bit values). */ /* aka: type & 248 == 8. Incidentally, 248 is equal to -8 in signed 8bit*/ and_reg_imm(in,-8); /* jz(not) -- saves one comparison in most cases, adds code size, more jumps. */ cmp_reg_imm(in,MIN_REF_TYPE); jne( not ); } static void mem_svalue_is_referenced(enum amd64_reg in, struct label *not ) { /* bit 4 set, and no higher bit set. */ if( in == P_REG_RAX ) Pike_error("RAX not supported here.\n"); mov_sval_type(in,P_REG_RAX); svalue_is_referenced(P_REG_RAX, not ); } #endif static void update_arg1(INT32 value) { mov_imm_reg(value, ARG1_REG); /* FIXME: Alloc stack space on NT. */ } static void update_arg2(INT32 value) { mov_imm_reg(value, ARG2_REG); /* FIXME: Alloc stack space on NT. */ } static void amd64_add_sp( int num ) { amd64_load_sp_reg(); add_reg_imm( sp_reg, num * sizeof(struct svalue)); dirty_regs |= 1 << PIKE_SP_REG; flush_dirty_regs(); /* FIXME: Need to change LABEL handling to remove this */ } static void amd64_add_mark_sp( int num ) { amd64_load_mark_sp_reg(); add_reg_imm( mark_sp_reg, num * sizeof(struct svalue*)); dirty_regs |= 1 << PIKE_MARK_SP_REG; flush_dirty_regs(); /* FIXME: Need to change LABEL handling to remove this */ } /* Note: Uses RAX and RCX internally. reg MUST not be P_REG_RAX. */ static void amd64_push_svaluep_to(int reg, int spoff) { LABELS(); if( reg == P_REG_RAX ) Pike_fatal("Using RAX in push_svaluep not supported\n" ); amd64_load_sp_reg(); mov_mem_reg(reg, OFFSETOF(svalue, tu.t.type), P_REG_RAX); mov_mem_reg(reg, OFFSETOF(svalue, u.refs), P_REG_RCX); mov_reg_mem(P_REG_RAX, sp_reg, SVAL(spoff).type); mov_reg_mem(P_REG_RCX, sp_reg, SVAL(spoff).value); and_reg32_imm(P_REG_RAX, MIN_REF_TYPE); jz(&label_A); add_imm_mem( 1, P_REG_RCX, OFFSETOF(pike_string, refs)); LABEL_A; } static void amd64_push_svaluep(int reg) { amd64_push_svaluep_to( reg, 0 ); amd64_add_sp( 1 ); } static void amd64_push_int(INT64 value, int subtype) { amd64_load_sp_reg(); mov_imm_mem((subtype<<16) + PIKE_T_INT, sp_reg, SVAL(0).type); mov_imm_mem(value, sp_reg, SVAL(0).value); amd64_add_sp( 1 ); } static void amd64_push_int_reg(enum amd64_reg reg ) { amd64_load_sp_reg(); mov_imm_mem( PIKE_T_INT, sp_reg, OFFSETOF(svalue, tu.t.type)); mov_reg_mem( reg, sp_reg, OFFSETOF(svalue, u.integer)); amd64_add_sp( 1 ); } static void amd64_get_storage( enum amd64_reg reg, ptrdiff_t offset ) { amd64_load_fp_reg(); #if 1 /* Note: We really should keep pike_frame->current_storage up to date instead.. */ mov_mem_reg( fp_reg, OFFSETOF(pike_frame,current_storage), reg ); add_reg_imm( reg, offset ); #else /* fp->current_object->storage */ mov_mem_reg(fp_reg, OFFSETOF(pike_frame, current_object), P_REG_RAX); mov_mem_reg(P_REG_RAX, OFFSETOF(object,storage), reg ); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, context), P_REG_RAX); /* + fp->context->storage_offset */ add_reg_mem( reg, P_REG_RAX, OFFSETOF(inherit,storage_offset) ); /* + offset */ add_reg_imm( reg, offset); #endif } static void amd64_mark(int offset) { amd64_load_sp_reg(); amd64_load_mark_sp_reg(); if (offset) { add_reg_imm_reg(sp_reg, -offset * sizeof(struct svalue), P_REG_RAX); mov_reg_mem(P_REG_RAX, mark_sp_reg, 0); } else { mov_reg_mem(sp_reg, mark_sp_reg, 0); } amd64_add_mark_sp( 1 ); } static void amd64_call_c_function(void *addr) { flush_dirty_regs(); call_imm(addr); } static void amd64_free_svalue_off(enum amd64_reg src, int off, int guaranteed_ref ) { LABELS(); if( src == P_REG_RAX ) Pike_fatal("Clobbering RAX for free-svalue\n"); /* load type -> RAX */ mov_mem8_reg( src, off, P_REG_RAX ); and_reg_imm(P_REG_RAX, MIN_REF_TYPE); jz( &label_A ); /* Load pointer to refs -> RAX */ mov_mem_reg( src,off+OFFSETOF(svalue, u.refs), P_REG_RAX); /* if( !--*RAX ) */ add_mem32_imm( P_REG_RAX, OFFSETOF(pike_string,refs), -1); if( !guaranteed_ref ) { /* We need to see if refs got to 0. */ jnz( &label_A ); /* if so, call really_free_svalue */ add_reg_imm_reg( src, off, ARG1_REG ); amd64_call_c_function(really_free_svalue); } LABEL_A; } static void amd64_free_svalue(enum amd64_reg src, int guaranteed_ref ) { amd64_free_svalue_off(src,0,guaranteed_ref); } /* Type already in register. Note: Clobbers the type register. */ static void amd64_free_svalue_type(enum amd64_reg src, enum amd64_reg type, int guaranteed_ref ) { LABELS(); /* if type < MIN_REF_TYPE+1 */ if( src == P_REG_RAX ) Pike_fatal("Clobbering RAX for free-svalue\n"); and_reg32_imm(type, MIN_REF_TYPE); jz( &label_A ); /* Load pointer to refs -> RAX */ mov_mem_reg( src, OFFSETOF(svalue, u.refs), P_REG_RAX); /* if( !--*RAX ) */ add_mem32_imm( P_REG_RAX, OFFSETOF(pike_string,refs), -1); if( !guaranteed_ref ) { /* We need to see if refs got to 0. */ jnz( &label_A ); /* if so, call really_free_svalue */ if( src != ARG1_REG ) mov_reg_reg( src, ARG1_REG ); amd64_call_c_function(really_free_svalue); } LABEL_A; } void amd64_ref_svalue( enum amd64_reg src, int already_have_type ) { LABELS(); if( src == P_REG_RAX ) Pike_fatal("Clobbering src in ref_svalue\n"); if( !already_have_type ) mov_sval_type( src, P_REG_RAX ); and_reg32_imm( P_REG_RAX, MIN_REF_TYPE ); jz( &label_A ); /* Load pointer to refs -> RAX */ mov_mem_reg( src, OFFSETOF(svalue, u.refs), P_REG_RAX); /* *RAX++ */ add_mem32_imm( P_REG_RAX, OFFSETOF(pike_string,refs), 1); LABEL_A; } void amd64_assign_svalue_no_free( enum amd64_reg dst, enum amd64_reg src, ptrdiff_t src_offset ) { if( dst == P_REG_RAX ||src == P_REG_RAX ) Pike_fatal( "Clobbering src/dst in amd64_assign_svalue_no_free <%d,%d>\n", dst, src); /* Copy src -> dst */ mov_mem_reg(src, src_offset, P_REG_RAX); mov_reg_mem(P_REG_RAX, dst, 0 ); mov_mem_reg(src, src_offset+sizeof(long), P_REG_RAX); mov_reg_mem(P_REG_RAX, dst, sizeof(long) ); } void amd64_assign_local( int b ) { amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame, locals), P_REG_RBX); add_reg_imm( P_REG_RBX, b*sizeof(struct svalue) ); amd64_free_svalue(P_REG_RBX, 0); amd64_assign_svalue_no_free( P_REG_RBX, sp_reg, -1*sizeof(struct svalue)); } static void amd64_pop_mark(void) { amd64_add_mark_sp( -1 ); } static void amd64_push_string(int strno, int subtype) { struct pike_string *str = Pike_compiler->new_program->strings[strno]; amd64_load_sp_reg(); mov_imm_reg((INT64)str,P_REG_RAX); mov_imm_mem((subtype<<16) | PIKE_T_STRING, sp_reg, SVAL(0).type); mov_reg_mem(P_REG_RAX,sp_reg,SVAL(0).value); add_imm_mem(1, P_REG_RAX,OFFSETOF(pike_string, refs)); amd64_add_sp(1); } static void amd64_push_local_function(int fun) { amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, context), P_REG_RAX); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, current_object),P_REG_RCX); mov_mem32_reg(P_REG_RAX, OFFSETOF(inherit, identifier_level), P_REG_RAX); mov_reg_mem(P_REG_RCX, sp_reg, OFFSETOF(svalue, u.object)); add_reg_imm(P_REG_RAX, fun); add_imm_mem(1, P_REG_RCX,(INT32)OFFSETOF(object, refs)); shl_reg_imm(P_REG_RAX, 16); add_reg_imm(P_REG_RAX, PIKE_T_FUNCTION); mov_reg_mem(P_REG_RAX, sp_reg, OFFSETOF(svalue, tu.t.type)); amd64_add_sp(1); } void amd64_update_pc(void) { INT32 tmp = PIKE_PC, disp; const enum amd64_reg tmp_reg = P_REG_RAX; if(amd64_prev_stored_pc == - 1) { amd64_load_fp_reg(); mov_rip_imm_reg(tmp - PIKE_PC, tmp_reg); mov_reg_mem(tmp_reg, fp_reg, OFFSETOF(pike_frame, pc)); #ifdef PIKE_DEBUG if (a_flag >= 60) fprintf (stderr, "pc %d update pc via lea\n", tmp); #endif amd64_prev_stored_pc = tmp; } else if ((disp = tmp - amd64_prev_stored_pc)) { #ifdef PIKE_DEBUG if (a_flag >= 60) fprintf (stderr, "pc %d update pc relative: %d\n", tmp, disp); #endif amd64_load_fp_reg(); mov_rip_imm_reg(tmp - PIKE_PC, tmp_reg); mov_reg_mem(tmp_reg, fp_reg, OFFSETOF(pike_frame, pc)); /* amd64_load_fp_reg(); */ /* add_imm_mem(disp, fp_reg, OFFSETOF (pike_frame, pc)); */ amd64_prev_stored_pc += disp; } else { #ifdef PIKE_DEBUG if (a_flag >= 60) fprintf (stderr, "pc %d update pc - already up-to-date\n", tmp); #endif } } static void maybe_update_pc(void) { static int last_prog_id=-1; static size_t last_num_linenumbers=-1; if( !store_pc ) return; if( #ifdef PIKE_DEBUG /* Update the pc more often for the sake of the opcode level trace. */ d_flag || #endif (amd64_prev_stored_pc == -1) || last_prog_id != Pike_compiler->new_program->id || last_num_linenumbers != Pike_compiler->new_program->num_linenumbers ) { last_prog_id=Pike_compiler->new_program->id; last_num_linenumbers = Pike_compiler->new_program->num_linenumbers; UPDATE_PC(); } } static void maybe_load_fp(void) { static int last_prog_id=-1; static size_t last_num_linenumbers=-1; if( !store_pc ) return; if( #ifdef PIKE_DEBUG /* Update the pc more often for the sake of the opcode level trace. */ d_flag || #endif (amd64_prev_stored_pc == -1) || last_prog_id != Pike_compiler->new_program->id || last_num_linenumbers != Pike_compiler->new_program->num_linenumbers ) { amd64_load_fp_reg(); } } static void sync_registers(int flags) { maybe_update_pc(); flush_dirty_regs(); if (flags & I_UPDATE_SP) sp_reg = P_REG_INVALID; if (flags & I_UPDATE_M_SP) mark_sp_reg = P_REG_INVALID; if (flags & I_UPDATE_FP) fp_reg = P_REG_INVALID; } static void amd64_call_c_opcode(void *addr, int flags) { sync_registers(flags); call_imm( addr ); } #ifdef PIKE_DEBUG static void ins_debug_instr_prologue (PIKE_INSTR_T instr, INT32 arg1, INT32 arg2) { int flags = instrs[instr].flags; /* Note: maybe_update_pc() is called by amd64_call_c_opcode() above, * which has the side-effect of loading fp_reg. Some of the * opcodes use amd64_call_c_opcode() in conditional segments. * This is to make sure that fp_reg is always loaded on exit * from such opcodes. */ maybe_load_fp(); /* For now: It is very hard to read the disassembled source when this is inserted */ if( !d_flag ) return; maybe_update_pc(); if (flags & I_HASARG2) mov_imm_reg(arg2, ARG3_REG); if (flags & I_HASARG) mov_imm_reg(arg1, ARG2_REG); mov_imm_reg(instr, ARG1_REG); if (flags & I_HASARG2) amd64_call_c_function (simple_debug_instr_prologue_2); else if (flags & I_HASARG) amd64_call_c_function (simple_debug_instr_prologue_1); else amd64_call_c_function (simple_debug_instr_prologue_0); } #else /* !PIKE_DEBUG */ #define ins_debug_instr_prologue(instr, arg1, arg2) maybe_load_fp() #endif static void amd64_push_this_object( ) { amd64_load_fp_reg(); amd64_load_sp_reg(); mov_imm_mem( PIKE_T_OBJECT, sp_reg, OFFSETOF(svalue, tu.t.type)); mov_mem_reg( fp_reg, OFFSETOF(pike_frame, current_object), P_REG_RAX ); mov_reg_mem( P_REG_RAX, sp_reg, OFFSETOF(svalue,u.object) ); add_mem32_imm( P_REG_RAX, (INT32)OFFSETOF(object, refs), 1); amd64_add_sp( 1 ); } static void amd64_align() { while( PIKE_PC & 3 ) ib( 0x90 ); } static void amd64_ins_branch_check_threads_etc(int code_only) { LABELS(); if( !branch_check_threads_update_etc ) { /* Create update + call to branch_check_threads_etc */ if( !code_only ) jmp( &label_A ); branch_check_threads_update_etc = PIKE_PC; if( (unsigned long long)&fast_check_threads_counter < 0x7fffffffULL ) { /* Short pointer. */ clear_reg( P_REG_RAX ); add_mem32_imm( P_REG_RAX, (int)(ptrdiff_t)&fast_check_threads_counter, 0x80 ); } else { mov_imm_reg( (long)&fast_check_threads_counter, P_REG_RAX); add_mem_imm( P_REG_RAX, 0, 0x80 ); } mov_imm_reg( (ptrdiff_t)branch_check_threads_etc, P_REG_RAX ); jmp_reg(P_REG_RAX); /* ret in BCTE will return to desired point. */ amd64_align(); } if( !code_only ) { LABEL_A; /* Use C-stack for counter. We have padding added in entry */ #ifndef USE_VALGRIND add_mem8_imm( P_REG_RSP, 0, 1 ); jno( &label_B ); #endif call_rel_imm32( branch_check_threads_update_etc ); #ifndef USE_VALGRIND LABEL_B; #endif } } void amd64_init_interpreter_state(void) { #ifdef PIKE_DEBUG if( PIKE_T_INT != 0 ) Pike_fatal("assumption failed: pike_t_int == 0\n"); if( sizeof(struct svalue) != 16 ) Pike_fatal("assumption failed: sizeof svalue != 16\n"); if( OFFSETOF(svalue,tu.t.type) != 0 ) Pike_fatal("assumption failed: offsetof(svalue.tu.t.type) != 0\n"); if( OFFSETOF(svalue,u.integer) != 8 ) Pike_fatal("assumption failed: offsetof(svalue.u.integer) != 8\n"); #endif instrs[F_CATCH - F_OFFSET].address = inter_return_opcode_F_CATCH; } static void amd64_return_from_function() { if( ret_for_func ) { jmp_rel_imm( ret_for_func ); } else { ret_for_func = PIKE_PC; pop(P_REG_RBX); /* Stack padding. */ pop(P_REG_RBX); pop(P_REG_R12); pop(P_REG_R13); pop(P_REG_R14); pop(P_REG_R15); pop(P_REG_RBP); ret(); } } static void if_not_two_int(struct label *to, int load) { amd64_load_sp_reg(); mov_mem8_reg(sp_reg, SVAL(-1).type, P_REG_RAX ); mov_mem8_reg(sp_reg, SVAL(-2).type, P_REG_RBX ); add_reg_reg(P_REG_RAX,P_REG_RBX); /* test_reg32(P_REG_RAX); int == 0 */ jnz(to); if( load ) { mov_mem_reg(sp_reg, SVAL(-1).value, P_REG_RAX ); mov_mem_reg(sp_reg, SVAL(-2).value, P_REG_RBX ); } } void ins_f_byte(unsigned int b) { int flags; void *addr; INT32 rel_addr = 0; LABELS(); b-=F_OFFSET; #ifdef PIKE_DEBUG if(b>255) Pike_error("Instruction too big %d\n",b); #endif maybe_update_pc(); flags = instrs[b].flags; addr=instrs[b].address; switch(b + F_OFFSET) { case F_DUP: ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); add_reg_imm_reg(sp_reg, -sizeof(struct svalue), P_REG_R10 ); amd64_push_svaluep( P_REG_R10 ); return; #if 0 case F_ESCAPE_CATCH: case F_EXIT_CATCH: ins_debug_instr_prologue(b, 0, 0); ins_f_byte( F_ESCAPE_CATCH ); amd64_load_sp_reg(); amd64_push_int( 0, 1 ); return; #endif /* -3 -2 -1 0 * lval[0], lval[1], <RANDOM>, **SP** * -> * -4 -3 -2 -1 0 * lval[0], lval[1], *lval, <RANDOM>, *SP** * * This will also free *lval iff it has type * array,multiset,mapping or string. */ case F_LTOSVAL2_AND_FREE: { ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -3*sizeof(struct svalue), P_REG_RBX ); cmp_reg_imm( P_REG_RBX, T_SVALUE_PTR ); jne( &label_A ); /* inline version for SVALUE_PTR. */ /* First, make room for the result, move top and inc sp */ mov_mem_reg( sp_reg, -sizeof(struct svalue), P_REG_RAX ); mov_mem_reg( sp_reg, -sizeof(struct svalue)+8, P_REG_RCX ); mov_reg_mem( P_REG_RAX, sp_reg, 0); mov_reg_mem( P_REG_RCX, sp_reg, 8); amd64_add_sp( 1 ); mov_mem_reg( sp_reg, -4*sizeof(struct svalue)+OFFSETOF(svalue,u.lval), P_REG_RBX ); amd64_push_svaluep_to(P_REG_RBX, -2); /* Result is now in sp[-2], lval in -4. */ /* push svaluep leaves type in RAX */ mov_reg_reg( P_REG_RAX, P_REG_RCX ); /* mov_mem8_reg( sp_reg, -2*sizeof(struct svalue), P_REG_RCX ); */ mov_imm_reg( 1, P_REG_RAX ); shl_reg32_reg( P_REG_RAX, P_REG_RCX ); and_reg_imm( P_REG_RAX, (BIT_ARRAY|BIT_MULTISET|BIT_MAPPING|BIT_STRING)); jz( &label_B ); /* Do nothing.. */ /* Free the old value. */ amd64_free_svalue( P_REG_RBX, 0 ); /* assign 0 */ mov_imm_mem( PIKE_T_INT, P_REG_RBX, 0 ); mov_imm_mem( 0, P_REG_RBX, 8 ); jmp( &label_B ); /* All done */ LABEL_A; /* So, not a svalueptr. Use C-version */ amd64_call_c_opcode( addr, flags ); amd64_load_sp_reg(); LABEL_B; } return; case F_LTOSVAL: { ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -sizeof(struct svalue)*2, P_REG_RAX ); /* lval type in RAX. */ /* if( rax == T_SVALUE_PTR ) push( *l->u.lval ) possibly: if( rax == T_OBJECT ) object_index_no_free( to, lval->u.object, lval->subtype, &lval[1]) if( rax == T_ARRAY && lval[1].type == PIKE_T_INT ) push( l->u.array->item[&lval[1].u.integer] ) */ cmp_reg_imm( P_REG_RAX, T_SVALUE_PTR ); je( &label_A ); /* So, not a svalueptr */ mov_reg_reg( sp_reg, ARG1_REG ); add_reg_imm_reg( sp_reg, -2*sizeof(struct svalue), ARG2_REG ); amd64_call_c_function(lvalue_to_svalue_no_free); amd64_load_sp_reg(); amd64_add_sp(1); jmp(&label_B); LABEL_A; mov_mem_reg( sp_reg, -sizeof(struct svalue)*2+OFFSETOF(svalue,u.lval), P_REG_RCX ); amd64_push_svaluep(P_REG_RCX); LABEL_B; } return; case F_ASSIGN: { ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -3*sizeof(struct svalue), P_REG_RAX ); cmp_reg_imm( P_REG_RAX, T_SVALUE_PTR ); je( &label_A ); /* So, not a svalueptr. Use C-version for simplicity */ amd64_call_c_opcode( addr, flags ); amd64_load_sp_reg(); jmp( &label_B ); amd64_align(); LABEL_A; mov_mem_reg( sp_reg, -3*sizeof(struct svalue)+8, P_REG_RBX ); /* Free old value. */ amd64_free_svalue( P_REG_RBX, 0 ); /* assign new value */ /* also move assigned value -> sp[-3] */ mov_mem_reg( sp_reg, -sizeof(struct svalue), P_REG_RAX ); mov_mem_reg( sp_reg, -sizeof(struct svalue)+8, P_REG_RCX ); mov_reg_mem( P_REG_RAX, P_REG_RBX, 0 ); mov_reg_mem( P_REG_RCX, P_REG_RBX, 8 ); add_reg_imm_reg( sp_reg, -sizeof(struct svalue), P_REG_RCX ); amd64_push_svaluep_to( P_REG_RCX, -3 ); /* Note: For SVALUEPTR we know we do not have to free the lvalue. */ amd64_add_sp( -2 ); LABEL_B; } return; case F_ASSIGN_AND_POP: { ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -3*sizeof(struct svalue), P_REG_RAX ); cmp_reg_imm( P_REG_RAX, T_SVALUE_PTR ); je( &label_A ); /* So, not a svalueptr. Use C-version for simplicity */ amd64_call_c_opcode( addr, flags ); amd64_load_sp_reg(); jmp( &label_B ); amd64_align(); LABEL_A; mov_mem_reg( sp_reg, -3*sizeof(struct svalue)+8, P_REG_RBX ); /* Free old value. */ amd64_free_svalue( P_REG_RBX, 0 ); /* assign new value */ mov_mem_reg( sp_reg, -sizeof(struct svalue), P_REG_RAX ); mov_mem_reg( sp_reg, -sizeof(struct svalue)+8, P_REG_RCX ); mov_reg_mem( P_REG_RAX, P_REG_RBX, 0 ); mov_reg_mem( P_REG_RCX, P_REG_RBX, 8 ); /* Note: For SVALUEPTR we know we do not have to free the lvalue. */ amd64_add_sp( -3 ); LABEL_B; } return; case F_NEGATE: { LABELS(); ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem8_reg(sp_reg, SVAL(-1).type, P_REG_RAX ); test_reg32(P_REG_RAX); jz(&label_B); jmp(&label_A); LABEL_D; neg_mem(sp_reg, SVAL(-1).value ); LABEL_A; amd64_call_c_opcode(addr, flags); jmp(&label_C); LABEL_B; mov_imm_mem(PIKE_T_INT, sp_reg, SVAL(-1).type ); neg_mem(sp_reg, SVAL(-1).value ); jo(&label_D); LABEL_C; } return; case F_NOT: { LABELS(); amd64_load_sp_reg(); mov_mem8_reg(sp_reg, SVAL(-1).type, P_REG_RCX ); test_reg32(P_REG_RCX); jz(&label_B); /* integer. */ mov_imm_reg( 1, P_REG_RAX ); shl_reg32_reg( P_REG_RAX, P_REG_RCX ); and_reg32_imm( P_REG_RAX, (BIT_FLOAT|BIT_ARRAY|BIT_MULTISET|BIT_MAPPING|BIT_STRING|BIT_PROGRAM)); jnz( &label_A ); /* object or function */ amd64_call_c_opcode(addr, flags); jmp(&label_C); /* int. */ LABEL_B; mov_mem_reg( sp_reg, SVAL(-1).value, P_REG_RAX ); clear_reg( P_REG_RCX ); cmp_reg_imm( P_REG_RAX, 0 ); set_if_eq(P_REG_RCX); mov_imm_mem( PIKE_T_INT, sp_reg, SVAL(-1).type ); mov_reg_mem( P_REG_RCX, sp_reg, SVAL(-1).value ); jmp(&label_C); LABEL_A; /* array etc, !x is always false */ amd64_free_svalue_off( sp_reg, SVAL(-1).off, 0 ); mov_imm_mem( PIKE_T_INT, sp_reg, SVAL(-1).type ); mov_imm_mem( 0, sp_reg, SVAL(-1).value ); LABEL_C; } return; case F_COMPL: { LABELS(); ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem8_reg(sp_reg, SVAL(-1).type, P_REG_RAX ); test_reg32(P_REG_RAX); jz(&label_B); LABEL_A; amd64_call_c_opcode(addr, flags); jmp(&label_C); LABEL_B; not_mem(sp_reg, SVAL(-1).value ); LABEL_C; } return; case F_MOD: case F_DIVIDE: { LABELS(); if_not_two_int(&label_A,0); mov_mem_reg(sp_reg, SVAL(-1).value, P_REG_RBX ); mov_mem_reg(sp_reg, SVAL(-2).value, P_REG_RAX ); cmp_reg_imm(P_REG_RAX, 0 ); jl(&label_A); if( b+F_OFFSET == F_MOD ) { /* Emulates pikes % functionality. */ cmp_reg_imm(P_REG_RBX, 0 ); jl(&label_A); } cmp_reg_imm(P_REG_RBX,0); je(&label_A); cmp_reg_imm(P_REG_RBX,-1); jne(&label_C); cmp_reg_imm(P_REG_RAX,0); jle(&label_A); /* FIXME: Int.native_min / -1 -> exception. This checks for -<whatever> / -1. There is bound to be a better way. Somehow disable the exception? Some SSE alternative that does not throw? Perhaps a 64/64->64 instead of the current 128/64->64? */ LABEL_C; div_reg_reg(P_REG_RAX,P_REG_RBX); mov_imm_mem(PIKE_T_INT, sp_reg, SVAL(-2).type); if( b+F_OFFSET == F_MOD ) mov_reg_mem(P_REG_RDX, sp_reg, SVAL(-2).value); else mov_reg_mem(P_REG_RAX, sp_reg, SVAL(-2).value); amd64_add_sp(-1); jmp(&label_B); LABEL_A; amd64_call_c_opcode(addr, flags); amd64_load_sp_reg(); LABEL_B; } return; case F_MULTIPLY: { LABELS(); if_not_two_int(&label_C,1); amd64_add_sp(-1); mul_rax_reg_reg128(P_REG_RBX); jo(&label_A); mov_imm_mem(PIKE_T_INT, sp_reg, SVAL(-1).type); /* Only needed for UNDEFINED*x -> 0 */ jmp(&label_B); LABEL_C; amd64_call_c_opcode(addr, flags); amd64_load_sp_reg(); jmp(&label_D); LABEL_A; /* overflows signed. upper 64 in edx, lower in eax. */ mov_reg_reg( P_REG_RAX, ARG1_REG ); mov_reg_reg( P_REG_RDX, ARG2_REG ); /* (on unix, not generated, arg2 is rdx) */ amd64_call_c_function(create_double_bignum); mov_imm_mem(PIKE_T_OBJECT, sp_reg, SVAL(-1).type); LABEL_B; mov_reg_mem(P_REG_RAX, sp_reg, SVAL(-1).value); LABEL_D; } return; case F_AND: { LABELS(); ins_debug_instr_prologue(b, 0, 0); if_not_two_int(&label_A,1); and_reg_reg(P_REG_RBX,P_REG_RAX); mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-2).type); mov_reg_mem(P_REG_RBX,sp_reg,SVAL(-2).value); amd64_add_sp(-1); jmp(&label_B); LABEL_A; amd64_call_c_opcode(addr, flags); amd64_load_sp_reg(); LABEL_B; } return; case F_OR: { LABELS(); ins_debug_instr_prologue(b, 0, 0); if_not_two_int(&label_A,1); or_reg_reg(P_REG_RAX,P_REG_RBX); mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-2).type); mov_reg_mem(P_REG_RBX,sp_reg,SVAL(-2).value); amd64_add_sp(-1); jmp(&label_B); LABEL_A; amd64_call_c_opcode(addr, flags); amd64_load_sp_reg(); LABEL_B; } return; case F_XOR: { LABELS(); ins_debug_instr_prologue(b, 0, 0); if_not_two_int(&label_A,1); xor_reg_reg(P_REG_RAX,P_REG_RBX); mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-2).type); mov_reg_mem(P_REG_RBX,sp_reg,SVAL(-2).value); amd64_add_sp(-1); jmp(&label_B); LABEL_A; amd64_call_c_opcode(addr, flags); amd64_load_sp_reg(); LABEL_B; } return; case F_RSH: { LABELS(); ins_debug_instr_prologue(b, 0, 0); if_not_two_int(&label_A,0); mov_mem_reg(sp_reg, SVAL(-1).value, P_REG_RCX ); cmp_reg_imm(P_REG_RCX,0); jl( &label_A ); cmp_reg_imm(P_REG_RCX,63); jl( &label_B ); LABEL_A; amd64_call_c_opcode(addr, flags); amd64_load_sp_reg(); jmp(&label_C); LABEL_B; mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-2).type); shr_mem_reg( sp_reg, SVAL(-2).value, P_REG_RCX); amd64_add_sp(-1); LABEL_C; } return; case F_LSH: { LABELS(); ins_debug_instr_prologue(b, 0, 0); if_not_two_int(&label_A,0); mov_mem_reg(sp_reg, SVAL(-1).value, P_REG_RCX ); cmp_reg_imm(P_REG_RCX,0); jl( &label_A ); cmp_reg_imm(P_REG_RCX,63); jl( &label_B ); LABEL_A; amd64_call_c_opcode(addr, flags); amd64_load_sp_reg(); jmp(&label_C); LABEL_B; mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-2).type); mov_mem_reg( sp_reg, SVAL(-2).value, P_REG_RBX); /* ok. It would have been nice is sal set a bit that stayed set when you shifted out a 1 bit. :) */ mov_reg_reg( P_REG_RBX, P_REG_RAX ); shl_reg_reg( P_REG_RBX, P_REG_RCX); mov_reg_reg( P_REG_RBX, P_REG_RDX ); shr_reg_reg( P_REG_RDX, P_REG_RCX ); cmp_reg_reg( P_REG_RDX, P_REG_RAX ); jne( &label_A ); mov_reg_mem( P_REG_RBX, sp_reg, SVAL(-2).value); amd64_add_sp(-1); LABEL_C; } return; case F_ADD_INTS: { ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem_reg( sp_reg, -sizeof(struct svalue)*2, P_REG_RAX ); add_reg_mem( P_REG_RAX, sp_reg, -sizeof(struct svalue ) ); jnz( &label_A ); /* So. Both are actually integers. */ mov_mem_reg( sp_reg, -sizeof(struct svalue)+OFFSETOF(svalue,u.integer), P_REG_RAX ); add_reg_mem( P_REG_RAX, sp_reg, -sizeof(struct svalue)*2+OFFSETOF(svalue,u.integer)); jo( &label_A ); amd64_add_sp( -1 ); /* the type only needs to be set if the subtype was set before. It was not, since the type check before would not have triggered. */ mov_reg_mem( P_REG_RAX, sp_reg, -sizeof(struct svalue)+OFFSETOF(svalue,u.integer)); jmp( &label_B ); LABEL_A; /* Fallback version */ update_arg1( 2 ); amd64_call_c_opcode( f_add, I_UPDATE_SP ); amd64_load_sp_reg(); LABEL_B; } return; case F_SWAP: /* pike_sp[-1] = pike_sp[-2] */ ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); add_reg_imm_reg( sp_reg, -2*sizeof(struct svalue), P_REG_RCX ); mov_mem128_reg( P_REG_RCX, 0, P_REG_XMM0 ); mov_mem128_reg( P_REG_RCX, 16, P_REG_XMM1 ); mov_reg_mem128( P_REG_XMM1, P_REG_RCX, 0 ); mov_reg_mem128( P_REG_XMM0, P_REG_RCX, 16 ); return; case F_INDEX: /* pike_sp[-2][pike_sp[-1]] */ ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -2*sizeof(struct svalue), P_REG_RAX ); mov_mem8_reg( sp_reg, -1*sizeof(struct svalue), P_REG_RBX ); shl_reg_imm( P_REG_RAX, 8 ); add_reg_reg( P_REG_RAX, P_REG_RBX ); mov_mem_reg( sp_reg, -1*sizeof(struct svalue)+8, P_REG_RBX ); /* int */ mov_mem_reg( sp_reg, -2*sizeof(struct svalue)+8, P_REG_RCX ); /* value */ cmp_reg32_imm( P_REG_RAX, (PIKE_T_ARRAY<<8)|PIKE_T_INT ); jne( &label_A ); /* Array and int index. */ mov_mem32_reg( P_REG_RCX, OFFSETOF(array,size), P_REG_RDX ); cmp_reg_imm( P_REG_RBX, 0 ); jge( &label_D ); /* less than 0, add size */ add_reg_reg( P_REG_RBX, P_REG_RDX ); LABEL_D; cmp_reg32_imm( P_REG_RBX, 0 ); jl( &label_B ); // <0 cmp_reg_reg( P_REG_RBX, P_REG_RDX); jge( &label_B ); // >size /* array, index inside array. push item, swap, pop, done */ push( P_REG_RCX ); /* Save array pointer */ mov_mem_reg( P_REG_RCX, OFFSETOF(array,item), P_REG_RCX ); shl_reg_imm( P_REG_RBX, 4 ); add_reg_reg( P_REG_RBX, P_REG_RCX ); /* This overwrites the array. */ amd64_add_sp( -1 ); amd64_push_svaluep_to( P_REG_RBX, -1 ); pop( P_REG_RCX ); /* We know it's an array. */ add_mem32_imm( P_REG_RCX, OFFSETOF(array,refs), -1); jnz( &label_C ); mov_reg_reg( P_REG_RCX, ARG1_REG ); amd64_call_c_function(really_free_array); jmp( &label_C ); LABEL_A; #if 0 cmp_reg32_imm( P_REG_RAX, (PIKE_T_STRING<<8)|PIKE_T_INT ); jne( &label_B ); #endif LABEL_B; /* something else. */ amd64_call_c_opcode( addr, flags ); amd64_load_sp_reg(); LABEL_C; /* done */ return; case F_SIZEOF_STRING: { LABELS(); ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, SVAL(-1).type, P_REG_RAX ); cmp_reg32_imm( P_REG_RAX, PIKE_T_STRING ); jne( &label_A ); mov_mem_reg( sp_reg, SVAL(-1).value, P_REG_RAX); mov_mem_reg( P_REG_RAX, OFFSETOF(pike_string,len), P_REG_RBX ); /* dec refs */ add_mem32_imm( P_REG_RAX, OFFSETOF(pike_string,refs), -1); jnz( &label_B ); /* no refs, call really_free_svalue */ add_reg_imm_reg( sp_reg, SVAL(-1).off, ARG1_REG ); amd64_call_c_function(really_free_svalue); jmp(&label_B); LABEL_A; /* not a string. */ amd64_call_c_opcode( addr, flags ); jmp(&label_C); LABEL_B; /* save size on stack. */ mov_imm_mem( PIKE_T_INT, sp_reg, SVAL(-1).type ); mov_reg_mem( P_REG_RBX, sp_reg, SVAL(-1).value ); LABEL_C; } return; case F_SIZEOF: { LABELS(); ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); add_reg_imm_reg( sp_reg, -sizeof(struct svalue), P_REG_RBX); mov_sval_type( P_REG_RBX, P_REG_RAX ); /* type in RAX, svalue in ARG1 */ cmp_reg32_imm( P_REG_RAX, PIKE_T_ARRAY ); jne( &label_A ); /* It's an array */ mov_mem_reg( P_REG_RBX, OFFSETOF(svalue, u.array ), ARG1_REG); /* load size -> RAX*/ mov_mem32_reg( ARG1_REG,OFFSETOF(array, size), P_REG_RAX ); jmp( &label_C ); LABEL_A; cmp_reg32_imm( P_REG_RAX, PIKE_T_STRING ); jne( &label_B ); /* It's a string */ mov_mem_reg( P_REG_RBX, OFFSETOF(svalue, u.string ), ARG1_REG); /* load size ->RAX*/ mov_mem32_reg( ARG1_REG,OFFSETOF(pike_string, len ), P_REG_RAX ); jmp( &label_C ); LABEL_B; /* It's something else, svalue in RBX. */ mov_reg_reg( P_REG_RBX, ARG1_REG ); amd64_call_c_function( pike_sizeof ); LABEL_C;/* all done, res in RAX */ /* free value, store result */ push( P_REG_RAX ); amd64_free_svalue( P_REG_RBX, 0 ); pop( P_REG_RAX ); mov_reg_mem(P_REG_RAX, P_REG_RBX, OFFSETOF(svalue, u.integer)); mov_imm_mem(PIKE_T_INT, P_REG_RBX, OFFSETOF(svalue, tu.t.type)); } return; case F_POP_VALUE: { ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); amd64_add_sp( -1 ); amd64_free_svalue( sp_reg, 0 ); } return; case F_CATCH: { /* Special argument for the F_CATCH instruction. */ addr = inter_return_opcode_F_CATCH; mov_rip_imm_reg(0, ARG1_REG); /* Address for the POINTER. */ rel_addr = PIKE_PC; } break; /* sp-1 = undefinedp(sp-1) */ case F_UNDEFINEDP: { LABELS(); ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem32_reg( sp_reg, SVAL(-1).type, P_REG_RAX ); cmp_reg32_imm( P_REG_RAX, 1<<16 | PIKE_T_INT ); jne( &label_A ); mov_imm_mem( 1, sp_reg,SVAL(-1).value); jmp( &label_B ); LABEL_A; amd64_free_svalue_off( sp_reg, SVAL(-1).off,0 ); mov_imm_mem( 0, sp_reg,SVAL(-1).value); LABEL_B; mov_imm_mem( PIKE_T_INT, sp_reg,SVAL(-1).type); } return; case F_ZERO_TYPE: { LABELS(); ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem32_reg( sp_reg, -sizeof(struct svalue), P_REG_RAX ); /* Rax now has type + subtype. */ mov_reg32_reg( P_REG_RAX, P_REG_RBX ); and_reg32_imm( P_REG_RAX, 0x1f ); cmp_reg32_imm( P_REG_RAX, PIKE_T_INT ); jne( &label_A ); /* It is an integer. */ shr_reg_imm( P_REG_RBX, 16 ); /* subtype in RBX. */ mov_imm_mem( PIKE_T_INT, sp_reg, -sizeof(struct svalue) ); mov_reg_mem( P_REG_RBX, sp_reg, -sizeof(struct svalue)+OFFSETOF(svalue,u.integer) ); jmp( &label_B ); LABEL_A; /* not an integer. Use C version for simplicitly.. */ amd64_call_c_opcode( addr, flags ); LABEL_B; } return; case F_EQ: case F_NE: /* Note: We can do better when doing equality comparison without much work. */ case F_LE: case F_GE: case F_LT: case F_GT: { LABELS(); ins_debug_instr_prologue(b, 0, 0); if_not_two_int(&label_A,1); amd64_add_sp(-1); clear_reg(P_REG_RCX); cmp_reg_reg(P_REG_RBX, P_REG_RAX); switch(b+F_OFFSET) { case F_GT: set_if_gt( P_REG_RCX); break; case F_LT: set_if_lt( P_REG_RCX); break; case F_LE: set_if_lte(P_REG_RCX );break; case F_GE: set_if_gte(P_REG_RCX ); break; case F_EQ: set_if_eq( P_REG_RCX ); break; case F_NE: set_if_neq(P_REG_RCX ); break; } mov_imm_mem(PIKE_T_INT, sp_reg, SVAL(-1).type ); mov_reg_mem(P_REG_RCX, sp_reg, SVAL(-1).value ); jmp(&label_D); LABEL_A; /* not an integer. Use C version for simplicitly.. */ amd64_call_c_opcode( addr, flags ); amd64_load_sp_reg(); LABEL_D; } return; case F_ADD: { addr = f_add; update_arg1(2); amd64_call_c_opcode(addr, flags); amd64_load_sp_reg(); } return; case F_SUBTRACT: { LABELS(); ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem8_reg(sp_reg, -1*sizeof(struct svalue), P_REG_RAX ); mov_mem8_reg(sp_reg, -2*sizeof(struct svalue), P_REG_RBX ); add_reg32_reg32(P_REG_RAX,P_REG_RBX); /* test_reg32(P_REG_RAX); int == 0 */ jnz(&label_A); #ifdef PIKE_DEBUG if( PIKE_T_INT ) Pike_fatal("Assertion failed\n"); #endif mov_mem_reg(sp_reg, -1*sizeof(struct svalue)+OFFSETOF(svalue,u.integer), P_REG_RAX ); mov_mem_reg(sp_reg, -2*sizeof(struct svalue)+OFFSETOF(svalue,u.integer), P_REG_RCX ); sub_reg_reg(P_REG_RCX,P_REG_RAX); jno(&label_B); LABEL_A; amd64_call_c_opcode(o_subtract, flags); amd64_load_sp_reg(); jmp(&label_C); LABEL_B; mov_reg_mem( P_REG_RCX, sp_reg, -2*sizeof(struct svalue)+OFFSETOF(svalue,u.integer)); amd64_add_sp(-1); LABEL_C; } return; case F_UNDEFINED: ins_debug_instr_prologue(b, 0, 0); amd64_push_int(0, 1); return; case F_CONST0: ins_debug_instr_prologue(b, 0, 0); amd64_push_int(0, 0); return; case F_CONST1: ins_debug_instr_prologue(b, 0, 0); amd64_push_int(1, 0); return; case F_CONST_1: ins_debug_instr_prologue(b, 0, 0); amd64_push_int(-1, 0); return; case F_BIGNUM: ins_debug_instr_prologue(b, 0, 0); amd64_push_int(0x7fffffff, 0); return; case F_RETURN_1: ins_f_byte(F_CONST1); ins_f_byte(F_RETURN); return; case F_RETURN_0: ins_f_byte(F_CONST0); ins_f_byte(F_RETURN); return; case F_MARK: case F_SYNCH_MARK: ins_debug_instr_prologue(b, 0, 0); amd64_mark(0); return; case F_MARK2: ins_f_byte(F_MARK); ins_f_byte(F_MARK); return; case F_MARK_AND_CONST0: ins_f_byte(F_MARK); ins_f_byte(F_CONST0); return; case F_MARK_AND_CONST1: ins_f_byte(F_MARK); ins_f_byte(F_CONST1); return; case F_POP_MARK: ins_debug_instr_prologue(b, 0, 0); amd64_pop_mark(); return; case F_POP_TO_MARK: ins_debug_instr_prologue(b, 0, 0); amd64_load_mark_sp_reg(); amd64_load_sp_reg(); amd64_pop_mark(); mov_mem_reg(mark_sp_reg, 0, P_REG_RBX); jmp(&label_A); LABEL_B; amd64_add_sp( -1 ); amd64_free_svalue( sp_reg, 0 ); amd64_load_sp_reg(); LABEL_A; cmp_reg_reg(P_REG_RBX, sp_reg); jl(&label_B); return; /* If we are compiling with debug, F_RETURN does extra checks */ case F_RETURN: case F_DUMB_RETURN: { LABELS(); ins_debug_instr_prologue(b, 0, 0); amd64_load_fp_reg(); /* Note: really mem16, but we & with PIKE_FRAME_RETURN_INTERNAL anyway */ mov_mem32_reg( fp_reg, OFFSETOF(pike_frame, flags), P_REG_RAX ); and_reg32_imm( P_REG_RAX, PIKE_FRAME_RETURN_INTERNAL); jnz( &label_A ); /* So, it is just a normal return. */ LABEL_B; /* Actually return */ flush_dirty_regs(); amd64_return_from_function(); /* */ LABEL_A; /* We should jump to the given address. */ mov_mem32_reg( fp_reg, OFFSETOF(pike_frame, flags), P_REG_RAX ); and_reg32_imm( P_REG_RAX, PIKE_FRAME_RETURN_POP ); jnz( &label_C ); amd64_call_c_function( low_return ); jmp( &label_D ); LABEL_C; amd64_call_c_function( low_return_pop ); LABEL_D; fp_reg = -1; amd64_load_fp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame, return_addr), P_REG_RAX ); jmp_reg( P_REG_RAX ); } return; case F_CLEAR_STRING_SUBTYPE: ins_debug_instr_prologue(b, 0, 0); amd64_load_sp_reg(); mov_mem32_reg(sp_reg, OFFSETOF(svalue, tu.t.type) - sizeof(struct svalue), P_REG_RAX); /* NB: We only care about subtype 1! */ cmp_reg32_imm(P_REG_RAX, (1<<16)|PIKE_T_STRING); jne(&label_A); and_reg32_imm(P_REG_RAX, 0x1f); mov_reg_mem32(P_REG_RAX, sp_reg, OFFSETOF(svalue, tu.t.type) - sizeof(struct svalue)); LABEL_A; return; } amd64_call_c_opcode(addr,flags); if (instrs[b].flags & I_RETURN) { LABELS(); if ((b + F_OFFSET) == F_RETURN_IF_TRUE) { /* Kludge. We must check if the ret addr is * PC + JUMP_EPILOGUE_SIZE. */ mov_rip_imm_reg(JUMP_EPILOGUE_SIZE, P_REG_RCX); } cmp_reg_imm(P_REG_RAX, -1); jne(&label_A); amd64_return_from_function(); LABEL_A; if ((b + F_OFFSET) == F_RETURN_IF_TRUE) { /* Kludge. We must check if the ret addr is * orig_addr + JUMP_EPILOGUE_SIZE. */ cmp_reg_reg( P_REG_RAX, P_REG_RCX ); je( &label_B ); jmp_reg(P_REG_RAX); LABEL_B; return; } } if (flags & I_JUMP) { jmp_reg(P_REG_RAX); if (b + F_OFFSET == F_CATCH) { upd_pointer(rel_addr - 4, PIKE_PC - rel_addr); } } } int amd64_ins_f_jump(unsigned int op, int backward_jump) { int flags; void *addr; int off = op - F_OFFSET; int ret = -1; LABELS(); #ifdef PIKE_DEBUG if(off>255) Pike_error("Instruction too big %d\n",off); #endif flags = instrs[off].flags; if (!(flags & I_BRANCH)) return -1; #define START_JUMP() do{ \ ins_debug_instr_prologue(off, 0, 0); \ if (backward_jump) { \ maybe_update_pc(); \ amd64_ins_branch_check_threads_etc(0); \ } \ } while(0) switch( op ) { case F_QUICK_BRANCH_WHEN_ZERO: case F_QUICK_BRANCH_WHEN_NON_ZERO: START_JUMP(); amd64_load_sp_reg(); amd64_add_sp( -1 ); mov_mem_reg( sp_reg, 8, P_REG_RAX ); test_reg32(P_REG_RAX); if( op == F_QUICK_BRANCH_WHEN_ZERO ) return jz_imm_rel32(0); return jnz_imm_rel32(0); case F_BRANCH_WHEN_ZERO: case F_BRANCH_WHEN_NON_ZERO: START_JUMP(); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -sizeof(struct svalue), P_REG_RCX ); cmp_reg32_imm( P_REG_RCX, PIKE_T_INT ); je( &label_C ); mov_imm_reg( 1, P_REG_RAX ); shl_reg32_reg( P_REG_RAX, P_REG_RCX ); and_reg32_imm( P_REG_RAX, BIT_FUNCTION|BIT_OBJECT ); jnz( &label_A ); /* string, array, mapping or float. Always true */ amd64_add_sp(-1); amd64_free_svalue_type( sp_reg, P_REG_RCX, 0 ); mov_imm_reg( 1, P_REG_RBX ); jmp( &label_B ); LABEL_A; /* function or object. Use svalue_is_true. */ add_reg_imm_reg(sp_reg, -sizeof(struct svalue), ARG1_REG ); amd64_call_c_function(svalue_is_true); amd64_load_sp_reg(); mov_reg_reg( P_REG_RAX, P_REG_RBX ); amd64_add_sp( -1 ); amd64_free_svalue( sp_reg, 0 ); /* Pop the stack. */ jmp( &label_B ); LABEL_C; /* integer */ mov_mem_reg( sp_reg, -sizeof(struct svalue)+OFFSETOF(svalue,u.integer), P_REG_RBX ); amd64_add_sp(-1); LABEL_B; /* Branch or not? */ test_reg( P_REG_RBX ); if( op == F_BRANCH_WHEN_ZERO ) return jz_imm_rel32(0); return jnz_imm_rel32(0); case F_FOREACH: START_JUMP(); /* -4: array -3: lvalue[0] -2: lvalue[1] -1: counter */ amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -4*sizeof(struct svalue), P_REG_RBX ); cmp_reg32_imm( P_REG_RBX, PIKE_T_ARRAY ); je(&label_D); /* Bad arg 1. Let the C opcode throw the error. */ amd64_call_c_opcode(instrs[off].address, flags); /* NOT_REACHED */ LABEL_D; mov_mem_reg( sp_reg, -1*sizeof(struct svalue)+8, P_REG_RAX ); mov_mem_reg( sp_reg, -4*sizeof(struct svalue)+8, P_REG_RBX ); mov_mem32_reg( P_REG_RBX, OFFSETOF(array,size), P_REG_RCX ); cmp_reg_reg( P_REG_RAX, P_REG_RCX ); jge(&label_A); /* increase counter */ add_mem_imm( sp_reg, -1*(int)sizeof(struct svalue)+8, 1 ); /* get item */ mov_mem_reg( P_REG_RBX, OFFSETOF(array,item), P_REG_RBX ); shl_reg_imm( P_REG_RAX, 4 ); add_reg_reg( P_REG_RBX, P_REG_RAX ); mov_mem8_reg( sp_reg, -3*sizeof(struct svalue), P_REG_RAX ); cmp_reg_imm( P_REG_RAX,T_SVALUE_PTR); jne( &label_C ); /* SVALUE_PTR optimization */ mov_mem_reg( sp_reg, -3*sizeof(struct svalue)+8, P_REG_RDX ); push( P_REG_RDX ); /* Free old value. */ amd64_free_svalue( P_REG_RDX, 0 ); pop( P_REG_RDX ); /* Assign new value. */ mov_mem_reg( P_REG_RBX, 0, P_REG_RAX ); mov_mem_reg( P_REG_RBX, 8, P_REG_RCX ); mov_reg_mem( P_REG_RAX, P_REG_RDX, 0 ); mov_reg_mem( P_REG_RCX, P_REG_RDX, 8 ); /* inc refs? */ and_reg32_imm( P_REG_RAX, MIN_REF_TYPE ); jz( &label_B ); add_imm_mem( 1, P_REG_RCX, OFFSETOF(pike_string, refs)); jmp( &label_B ); LABEL_C; add_reg_imm_reg( sp_reg, -3*sizeof(struct svalue), ARG1_REG ); mov_reg_reg( P_REG_RBX, ARG2_REG ); amd64_call_c_function( assign_lvalue ); jmp(&label_B); LABEL_A; mov_imm_reg( 0, P_REG_RBX ); LABEL_B; test_reg(P_REG_RBX); return jnz_imm_rel32(0); case F_LOOP: START_JUMP(); /* counter in pike_sp-1 */ /* decrement until 0. */ /* if not 0, branch */ /* otherwise, pop */ amd64_load_sp_reg(); mov_mem32_reg( sp_reg, SVAL(-1).type, P_REG_RAX ); /* Is it a normal integer? subtype -> 0, type -> PIKE_T_INT */ cmp_reg32_imm( P_REG_RAX, PIKE_T_INT ); jne( &label_A ); /* if it is, is it <= 0? */ mov_mem_reg( sp_reg, SVAL(-1).value, P_REG_RAX ); cmp_reg_imm(P_REG_RAX,0); jle(&label_B); /* it is. */ /* add_reg_imm( P_REG_RAX, -1 ); */ /* mov_reg_mem( P_REG_RAX, sp_reg, -sizeof(struct svalue)+8); */ add_mem_imm( sp_reg, SVAL(-1).value, -1 ); /* REG_RAX known true, so no need to set it to 1. */ /* mov_imm_reg( 1, P_REG_RAX ); */ /* decremented. Jump -> true. */ /* This is where we would really like to have two instances of * the target returned from this function... */ jmp( &label_C ); LABEL_A; /* Not an integer. */ amd64_call_c_opcode(instrs[F_LOOP-F_OFFSET].address, instrs[F_LOOP-F_OFFSET].flags ); amd64_load_sp_reg(); jmp( &label_C ); /* result in RAX */ LABEL_B; /* loop done, inline. Known to be int, and 0 */ amd64_add_sp( -1 ); mov_imm_reg(0, P_REG_RAX ); LABEL_C; /* Branch or not? */ test_reg( P_REG_RAX ); return jnz_imm_rel32(0); case F_BRANCH_WHEN_EQ: /* sp[-2] != sp[-1] */ case F_BRANCH_WHEN_NE: /* sp[-2] != sp[-1] */ /* START_JUMP();*/ ins_debug_instr_prologue(op, 0, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -sizeof(struct svalue), P_REG_RCX ); mov_mem8_reg( sp_reg, -sizeof(struct svalue)*2,P_REG_RBX ); cmp_reg_reg( P_REG_RCX, P_REG_RBX ); jnz( &label_A ); /* Types differ */ /* Fallback to C for functions, objects and floats. */ mov_imm_reg(1, P_REG_RBX); shl_reg32_reg(P_REG_RBX, P_REG_RCX); and_reg_imm(P_REG_RBX, (BIT_FUNCTION|BIT_OBJECT|BIT_FLOAT)); jnz( &label_A ); mov_mem_reg( sp_reg, -sizeof(struct svalue)+8, P_REG_RBX ); sub_reg_mem( P_REG_RBX, sp_reg, -sizeof(struct svalue)*2+8); /* RBX will now be 0 if they are equal.*/ /* Optimization: The types are equal, pop_stack can be greatly * simplified if they are <= max_ref_type */ cmp_reg32_imm( P_REG_RCX,MIN_REF_TYPE); jge( &label_B ); /* cheap pop. We know that both are > max_ref_type */ amd64_add_sp( -2 ); jmp( &label_D ); LABEL_A; /* Fallback - call opcode. */ amd64_call_c_opcode( instrs[F_BRANCH_WHEN_NE-F_OFFSET].address, instrs[F_BRANCH_WHEN_NE-F_OFFSET].flags ); amd64_load_sp_reg(); /* Opcode returns 0 if equal, -1 if not. */ mov_reg_reg(P_REG_RAX, P_REG_RBX); jmp(&label_D); LABEL_B; /* comparison done, pop stack x2, reftypes */ amd64_add_sp( -2 ); mov_mem_reg( sp_reg, OFFSETOF(svalue,u.refs), P_REG_RAX ); add_mem32_imm( P_REG_RAX, OFFSETOF(pike_string,refs), -1 ); jnz( &label_C ); /* Free sp_reg */ mov_reg_reg( sp_reg, ARG1_REG ); amd64_call_c_function( really_free_svalue ); amd64_load_sp_reg(); LABEL_C; add_reg_imm_reg( sp_reg, sizeof(struct svalue), ARG1_REG ); mov_mem_reg( ARG1_REG, OFFSETOF(svalue,u.refs), P_REG_RAX ); add_mem32_imm( P_REG_RAX, OFFSETOF(pike_string,refs), -1 ); jnz( &label_D ); amd64_call_c_function( really_free_svalue ); /* free sp[-2] */ LABEL_D; test_reg(P_REG_RBX); if( op == F_BRANCH_WHEN_EQ ) return jz_imm_rel32(0); return jnz_imm_rel32(0); #if 0 case F_BRANCH_WHEN_LT: /* sp[-2] < sp[-1] */ case F_BRANCH_WHEN_GE: /* sp[-2] >= sp[-1] */ case F_BRANCH_WHEN_GT: /* sp[-2] > sp[-1] */ case F_BRANCH_WHEN_LE: /* sp[-2] <= sp[-1] */ #endif case F_BRANCH: START_JUMP(); add_to_program(0xe9); ret=(INT32) PIKE_PC; PUSH_INT(0); return ret; } maybe_update_pc(); addr=instrs[off].address; amd64_call_c_opcode(addr, flags); amd64_load_sp_reg(); test_reg(P_REG_RAX); if (backward_jump) { INT32 skip; add_to_program (0x74); /* jz rel8 */ add_to_program (0); /* Bytes to skip. */ skip = (INT32)PIKE_PC; amd64_ins_branch_check_threads_etc(0); add_to_program (0xe9); /* jmp rel32 */ ret = (INT32) PIKE_PC; PUSH_INT (0); /* Adjust the skip for the relative jump. */ Pike_compiler->new_program->program[skip-1] = ((INT32)PIKE_PC - skip); } else { add_to_program (0x0f); /* jnz rel32 */ add_to_program (0x85); ret = (INT32) PIKE_PC; PUSH_INT (0); } return ret; } void ins_f_byte_with_arg(unsigned int a, INT32 b) { maybe_update_pc(); switch(a) { case F_THIS_OBJECT: if( b == 0 ) { ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_push_this_object(); return; } break; /* Fallback to C-version. */ case F_POP_N_ELEMS: { int i; LABELS(); ins_debug_instr_prologue(a-F_OFFSET,b, 0); amd64_load_sp_reg(); if( b < 3 ) { for(i=0;i<b;i++) amd64_free_svalue_off( sp_reg, SVAL(-1-i).off, 0 ); amd64_add_sp( -b ); return; } break; /* use c version. */ /* FIXME: Why does not this work? */ /* add_reg_imm_reg( sp_reg, -SVAL(b).off, P_REG_RBX ); */ /* LABEL_A; */ /* amd64_free_svalue_off( sp_reg, SVAL(-1).off,0 ); */ /* amd64_add_sp( -1 ); */ /* cmp_reg_reg(P_REG_RBX,sp_reg); */ /* jne(&label_A); */ } return; case F_RETURN_LOCAL: /* FIXME: The C version has a trick: if locals+b < expendibles, pop to there and return. This saves a push, and the poping has to be done anyway. */ ins_f_byte_with_arg( F_LOCAL, b ); ins_f_byte( F_DUMB_RETURN ); return; case F_NEG_INT_INDEX: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -1*sizeof(struct svalue), P_REG_RAX ); cmp_reg32_imm( P_REG_RAX, PIKE_T_ARRAY ); jne( &label_A ); mov_mem_reg( sp_reg, -1*sizeof(struct svalue)+8, P_REG_RDX ); /* u.array */ /* -> arr[sizeof(arr)-b] */ mov_mem32_reg( P_REG_RDX, OFFSETOF(array,size), P_REG_RBX ); sub_reg_imm( P_REG_RBX, b ); js( &label_A ); /* if signed result, index outside array */ shl_reg_imm( P_REG_RBX, 4 ); add_reg_mem( P_REG_RBX, P_REG_RDX, OFFSETOF(array,item) ); /* This overwrites the array. */ amd64_push_svaluep_to( P_REG_RBX, -1 ); /* We know it's an array. */ add_mem32_imm( P_REG_RDX, OFFSETOF(array,refs), -1); jnz( &label_C ); mov_reg_reg( P_REG_RDX, ARG1_REG ); amd64_call_c_function(really_free_array); jmp( &label_C ); LABEL_A; update_arg1( b ); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_C; } return; case F_POS_INT_INDEX: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg, -1*sizeof(struct svalue), P_REG_RAX ); cmp_reg32_imm( P_REG_RAX, PIKE_T_ARRAY ); jne( &label_A ); mov_mem_reg( sp_reg, -1*sizeof(struct svalue)+8, P_REG_RDX ); /* u.array */ /* -> arr[sizeof(arr)-b] */ mov_mem32_reg( P_REG_RDX, OFFSETOF(array,size), P_REG_RCX ); cmp_reg32_imm( P_REG_RCX, b ); jle( &label_A ); /* RCX <= b, index outside array */ mov_imm_reg( b * sizeof(struct svalue), P_REG_RBX); add_reg_mem( P_REG_RBX, P_REG_RDX, OFFSETOF(array,item) ); /* This overwrites the array. */ amd64_push_svaluep_to( P_REG_RBX, -1 ); /* We know it's an array. */ add_mem32_imm( P_REG_RDX, OFFSETOF(array,refs), -1); jnz( &label_C ); mov_reg_reg( P_REG_RDX, ARG1_REG ); amd64_call_c_function(really_free_array); jmp( &label_C ); LABEL_A; update_arg1( b ); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_C; } return; case F_LOCAL_INDEX: { LABELS(); /* local[pike_sp[-1]] */ ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); amd64_load_fp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame,locals), P_REG_RDX); add_reg_imm( P_REG_RDX, b*sizeof(struct svalue)); mov_mem8_reg( P_REG_RDX, 0, P_REG_RAX ); mov_mem8_reg( sp_reg, -1*sizeof(struct svalue), P_REG_RBX ); shl_reg_imm( P_REG_RAX, 8 ); add_reg_reg( P_REG_RAX, P_REG_RBX ); mov_mem_reg( sp_reg, -1*sizeof(struct svalue)+8, P_REG_RBX ); /* int */ mov_mem_reg( P_REG_RDX, 8, P_REG_RCX ); /* value */ cmp_reg32_imm( P_REG_RAX, (PIKE_T_ARRAY<<8)|PIKE_T_INT ); jne( &label_A ); /* Array and int index. */ mov_mem32_reg( P_REG_RCX, OFFSETOF(array,size), P_REG_RDX ); cmp_reg32_imm( P_REG_RBX, 0 ); jge( &label_D ); /* less than 0, add size */ add_reg_reg( P_REG_RBX, P_REG_RDX ); LABEL_D; cmp_reg32_imm( P_REG_RBX, 0 ); jl( &label_B ); // <0 cmp_reg_reg( P_REG_RBX, P_REG_RCX); jge( &label_B ); // >=size /* array, index inside array. push item, swap, pop, done */ mov_mem_reg( P_REG_RCX, OFFSETOF(array,item), P_REG_RCX ); shl_reg_imm( P_REG_RBX, 4 ); add_reg_reg( P_REG_RBX, P_REG_RCX ); amd64_push_svaluep_to( P_REG_RBX, -1 ); jmp( &label_C ); LABEL_A; #if 0 cmp_reg32_imm( P_REG_RAX, (PIKE_T_STRING<<8)|PIKE_T_INT ); jne( &label_B ); #endif LABEL_B; /* something else. */ update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_C; /* done */ } return; case F_MULTIPLY_INT: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); mov_mem8_reg(sp_reg, SVAL(-1).type, P_REG_RAX ); test_reg32(P_REG_RAX); jnz(&label_A); /* FIXME: mul_reg_mem_imm actually exists as an instruction. */ mov_imm_reg(b, P_REG_RAX); mov_mem_reg(sp_reg, SVAL(-1).value, P_REG_RBX ); mul_reg_reg(P_REG_RBX,P_REG_RAX); jo(&label_A); mov_imm_mem(PIKE_T_INT, sp_reg, SVAL(-1).type); mov_reg_mem(P_REG_RBX, sp_reg, SVAL(-1).value); jmp(&label_B); LABEL_A; update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_B; } return; case F_MOD_INT: if( b < 0 ) break; /* FALL_THROUGH */ case F_DIVIDE_INT: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); mov_mem8_reg(sp_reg,SVAL(-1).type, P_REG_RAX); test_reg32(P_REG_RAX); jnz(&label_A); mov_mem_reg(sp_reg, SVAL(-1).value, P_REG_RAX); if( b == -1 ) { /* 64bit imm not done. */ cmp_reg_imm(P_REG_RAX,-0x80000000); jle(&label_A); } /*if( a == F_MOD_INT )*/ { cmp_reg_imm(P_REG_RAX, 0); jl(&label_A); } mov_imm_reg(b,P_REG_RBX); div_reg_reg(P_REG_RAX,P_REG_RBX); mov_imm_mem(PIKE_T_INT, sp_reg, SVAL(-1).type); if( a == F_MOD_INT ) mov_reg_mem(P_REG_RDX, sp_reg, SVAL(-1).value); else mov_reg_mem(P_REG_RAX, sp_reg, SVAL(-1).value); jmp(&label_B); LABEL_A; update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_B; } return; case F_AND_INT: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET,b, 0); amd64_load_sp_reg(); mov_mem8_reg(sp_reg, SVAL(-1).type, P_REG_RAX ); test_reg32(P_REG_RAX); jnz(&label_A); /* FIXME: and_mem_imm */ mov_mem_reg(sp_reg, SVAL(-1).value, P_REG_RAX ); and_reg_imm(P_REG_RAX,b); mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-1).type); mov_reg_mem(P_REG_RAX,sp_reg,SVAL(-1).value); jmp(&label_B); LABEL_A; update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_B; } return; case F_XOR_INT: { LABELS(); amd64_load_sp_reg(); ins_debug_instr_prologue(a,b,0); mov_mem8_reg(sp_reg,SVAL(-1).type, P_REG_RAX); test_reg32(P_REG_RAX); jnz(&label_A); mov_mem_reg(sp_reg,SVAL(-1).value, P_REG_RAX); mov_imm_reg(b,P_REG_RBX); xor_reg_reg(P_REG_RAX,P_REG_RBX); mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-1).type); mov_reg_mem(P_REG_RBX,sp_reg,SVAL(-1).value); jmp(&label_B); LABEL_A; update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_B; } return; case F_OR_INT: if( !b ) return; { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); mov_mem8_reg(sp_reg, SVAL(-1).type, P_REG_RAX ); test_reg32(P_REG_RAX); jnz(&label_A); /* FIXME: or_mem_imm */ mov_mem_reg(sp_reg, SVAL(-1).value, P_REG_RAX ); or_reg_imm(P_REG_RAX,b); mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-1).type); mov_reg_mem(P_REG_RAX,sp_reg,SVAL(-1).value); jmp(&label_B); LABEL_A; update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_B; } return; case F_LSH_INT: if( b > 0 && b <= 63 ) { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); mov_mem8_reg(sp_reg, SVAL(-1).type, P_REG_RAX ); test_reg32(P_REG_RAX); jz(&label_B); LABEL_A; update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); jmp(&label_C); LABEL_B; mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-1).type); mov_mem_reg( sp_reg, SVAL(-1).value, P_REG_RBX); /* ok. It would have been nice is sal set a bit that stayed set when you shifted out a 1 bit. :) */ mov_reg_reg( P_REG_RBX, P_REG_RAX ); shl_reg_imm( P_REG_RBX, b); mov_reg_reg( P_REG_RBX, P_REG_RDX ); shr_reg_imm( P_REG_RDX, b ); cmp_reg_reg( P_REG_RDX, P_REG_RAX ); jne( &label_A ); mov_reg_mem( P_REG_RBX, sp_reg, SVAL(-1).value); LABEL_C; return; } if(!b) return; if( b < 0 ) yyerror("<< with negative constant\n"); break; case F_RSH_INT: if( b > 0 && b <= 63 ) { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); mov_mem8_reg(sp_reg, SVAL(-1).type, P_REG_RAX ); test_reg32(P_REG_RAX); jnz(&label_A); mov_mem_reg( sp_reg, SVAL(-1).value, P_REG_RAX); /* FIXME: shr_mem_imm */ mov_imm_mem(PIKE_T_INT,sp_reg,SVAL(-1).type); shr_reg_imm( P_REG_RAX, b); mov_reg_mem( P_REG_RAX, sp_reg, SVAL(-1).value); jmp(&label_B); LABEL_A; update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_B; return; } if(!b) return; if( b < 0 ) yyerror(">> with negative constant\n"); break; case F_SUBTRACT_INT: case F_ADD_NEG_INT: b = -b; /* FALL_THROUGH */ case F_ADD_INT: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); mov_mem8_reg( sp_reg,SVAL(-1).type, P_REG_RAX ); test_reg32(P_REG_RAX); jnz( &label_A ); mov_mem_reg(sp_reg, SVAL(-1).value,P_REG_RAX ); add_reg_imm( P_REG_RAX, b ); jo( &label_A ); /* if overflow, use f_add */ mov_imm_mem( PIKE_T_INT, sp_reg, SVAL(-1).type ); mov_reg_mem( P_REG_RAX, sp_reg, SVAL(-1).value ); jmp(&label_B); /* all done. */ LABEL_A; amd64_push_int(b,0); update_arg1(2); amd64_call_c_opcode( f_add, I_UPDATE_SP ); amd64_load_sp_reg(); LABEL_B; } return; case F_NUMBER: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_push_int(b, 0); return; case F_NEG_NUMBER: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_push_int(-(INT64)b, 0); return; case F_STRING: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_push_string(b, 0); return; case F_ARROW_STRING: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_push_string(b, 1); return; case F_MARK_AND_CONST0: ins_f_byte(F_MARK); ins_f_byte(F_CONST0); return; case F_MARK_AND_CONST1: ins_f_byte(F_MARK); ins_f_byte(F_CONST0); return; case F_MARK_AND_STRING: ins_f_byte(F_MARK); ins_f_byte_with_arg(F_STRING, b); return; case F_MARK_AND_GLOBAL: ins_f_byte(F_MARK); ins_f_byte_with_arg(F_GLOBAL, b); return; case F_MARK_AND_LOCAL: ins_f_byte(F_MARK); ins_f_byte_with_arg(F_LOCAL, b); return; case F_MARK_X: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_mark(b); return; case F_LFUN: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_push_local_function(b); return; case F_ASSIGN_LOCAL: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); amd64_assign_local(b); add_reg_imm_reg(sp_reg, -sizeof(struct svalue), ARG1_REG); amd64_ref_svalue(ARG1_REG, 0); return; case F_ASSIGN_LOCAL_AND_POP: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_assign_local(b); amd64_add_sp(-1); return; case F_ASSIGN_PRIVATE_GLOBAL_AND_POP: case F_ASSIGN_PRIVATE_GLOBAL: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_get_storage( P_REG_RBX, b ); /* do not assign if this object is destructed. */ mov_mem_reg( fp_reg, OFFSETOF(pike_frame,current_object), ARG1_REG ); mov_mem_reg( ARG1_REG, OFFSETOF(object,prog), P_REG_RAX ); test_reg(P_REG_RAX); jnz(&label_A); /* Note: will throw error ('cannot index destructed object' or similar). * Note: Only arg1 is correct here (points to the destructed object) */ amd64_call_c_function(object_low_set_index); LABEL_A; amd64_free_svalue( P_REG_RBX, 0 ); amd64_load_sp_reg(); if( a == F_ASSIGN_PRIVATE_GLOBAL_AND_POP ) { amd64_add_sp(-1); amd64_assign_svalue_no_free( P_REG_RBX, sp_reg, 0); } else { amd64_assign_svalue_no_free( P_REG_RBX, sp_reg, -sizeof(struct svalue)); amd64_ref_svalue(P_REG_RBX,0); } } return; case F_ASSIGN_GLOBAL: case F_ASSIGN_GLOBAL_AND_POP: /* arg1: pike_fp->current obj arg2: arg1+idenfier level arg3: Pike_sp-1 */ /* NOTE: We cannot simply do the same optimization as for ASSIGN_LOCAL_AND_POP with assign global, since assigning at times does not add references. We do know, however, that refs (should) never reach 0 when poping the stack. We can thus skip that part of pop_value */ ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, current_object), ARG1_REG); mov_mem_reg(fp_reg, OFFSETOF(pike_frame,context), ARG2_REG); mov_mem16_reg(ARG2_REG, OFFSETOF(inherit, identifier_level), ARG2_REG); add_reg_imm( ARG2_REG, b ); add_reg_imm_reg( sp_reg, -sizeof(struct svalue), ARG3_REG ); amd64_call_c_function( object_low_set_index ); if( a == F_ASSIGN_GLOBAL_AND_POP ) { /* assign done, pop. */ amd64_load_sp_reg(); amd64_add_sp( -1 ); amd64_free_svalue( sp_reg, 1 ); } return; case F_SIZEOF_LOCAL: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame,locals), ARG1_REG); add_reg_imm( ARG1_REG, b*sizeof(struct svalue)); mov_sval_type( ARG1_REG, P_REG_RAX ); /* type in RAX, svalue in ARG1 */ cmp_reg32_imm( P_REG_RAX, PIKE_T_ARRAY ); jne( &label_A ); /* It's an array */ /* move arg to point to the array */ mov_mem_reg( ARG1_REG, OFFSETOF(svalue, u.array ), ARG1_REG); /* load size -> RAX*/ mov_mem32_reg( ARG1_REG,OFFSETOF(array, size), P_REG_RAX ); jmp( &label_C ); LABEL_A; cmp_reg32_imm( P_REG_RAX, PIKE_T_STRING ); jne( &label_B ); /* It's a string */ /* move arg to point to the string */ mov_mem_reg( ARG1_REG, OFFSETOF(svalue, u.string ), ARG1_REG); /* load size ->RAX*/ mov_mem32_reg( ARG1_REG,OFFSETOF(pike_string, len ), P_REG_RAX ); jmp( &label_C ); LABEL_B; /* It's something else, svalue already in ARG1. */ amd64_call_c_function( pike_sizeof ); LABEL_C;/* all done, res in RAX */ /* Store result on stack */ amd64_push_int_reg( P_REG_RAX ); } return; case F_SIZEOF_LOCAL_STRING: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame,locals), ARG1_REG); add_reg_imm( ARG1_REG, b*sizeof(struct svalue)); mov_sval_type( ARG1_REG, P_REG_RAX ); mov_mem_reg( ARG1_REG, OFFSETOF(svalue, u.string ), P_REG_RBX); /* type in RAX, svalue in ARG1 */ cmp_reg32_imm( P_REG_RAX, PIKE_T_STRING ); je( &label_B ); /* It's something else, svalue already in ARG1. */ amd64_call_c_function( pike_sizeof ); jmp( &label_A ); LABEL_B; mov_mem32_reg( P_REG_RBX,OFFSETOF(pike_string, len ), P_REG_RAX ); /* Store result on stack */ LABEL_A; amd64_push_int_reg( P_REG_RAX ); } return; case F_PRIVATE_GLOBAL: /* This is a private (or final) global which is not a 'short' one. It is guaranteed to be available as an svalue at pike_fp->current_object->storage + pike_fp->context->storage_offset + offset (I really wish pike_fp->current_storage was kept up to date for pike function..) */ ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_sp_reg(); amd64_get_storage( P_REG_RBX, b ); amd64_push_svaluep( P_REG_RBX ); return; case F_GLOBAL: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, context), ARG3_REG); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, current_object), ARG2_REG); mov_reg_reg(sp_reg, ARG1_REG); mov_mem16_reg(ARG3_REG, OFFSETOF(inherit, identifier_level), ARG3_REG); add_reg_imm(ARG3_REG, b); amd64_call_c_function(low_object_index_no_free); amd64_add_sp(1); return; case F_LOCAL: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, locals), P_REG_RCX); add_reg_imm(P_REG_RCX, b*sizeof(struct svalue)); amd64_push_svaluep(P_REG_RCX); return; case F_CLEAR_LOCAL: ins_f_byte_with_2_args( F_CLEAR_N_LOCAL, b, 1 ); return; case F_INC_LOCAL_AND_POP: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, locals), P_REG_RCX); add_reg_imm(P_REG_RCX, b*sizeof(struct svalue)); mov_sval_type(P_REG_RCX, P_REG_RAX); cmp_reg32_imm(P_REG_RAX, PIKE_T_INT); jne(&label_A); /* Integer - Zap subtype and try just incrementing it. */ mov_reg_mem32(P_REG_RAX, P_REG_RCX, OFFSETOF(svalue, tu.t.type)); add_imm_mem(1, P_REG_RCX, OFFSETOF(svalue, u.integer)); jno(&label_B); add_imm_mem(-1, P_REG_RCX, OFFSETOF(svalue, u.integer)); LABEL_A; /* Fallback to the C-implementation. */ update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_B; } return; case F_INC_LOCAL: ins_f_byte_with_arg(F_INC_LOCAL_AND_POP, b); ins_f_byte_with_arg(F_LOCAL, b); return; case F_POST_INC_LOCAL: ins_f_byte_with_arg(F_LOCAL, b); ins_f_byte_with_arg(F_INC_LOCAL_AND_POP, b); return; case F_DEC_LOCAL_AND_POP: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, locals), P_REG_RCX); add_reg_imm(P_REG_RCX, b*sizeof(struct svalue)); mov_sval_type(P_REG_RCX, P_REG_RAX); cmp_reg32_imm(P_REG_RAX, PIKE_T_INT); jne(&label_A); /* Integer - Zap subtype and try just decrementing it. */ mov_reg_mem32(P_REG_RAX, P_REG_RCX, OFFSETOF(svalue, tu.t.type)); add_imm_mem(-1, P_REG_RCX, OFFSETOF(svalue, u.integer)); jno(&label_B); add_imm_mem(1, P_REG_RCX, OFFSETOF(svalue, u.integer)); LABEL_A; /* Fallback to the C-implementation. */ update_arg1(b); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_B; } return; case F_DEC_LOCAL: ins_f_byte_with_arg(F_DEC_LOCAL_AND_POP, b); ins_f_byte_with_arg(F_LOCAL, b); return; case F_POST_DEC_LOCAL: ins_f_byte_with_arg(F_LOCAL, b); ins_f_byte_with_arg(F_DEC_LOCAL_AND_POP, b); return; #if 0 /* These really have to be done inline: reg = (sp- *--mark_sp)>>16 ltosval_and_free(-(args+2)) -> pike_sp-args call_builtin(reg) -- stack now lvalue, result, so now.. ins_f_byte( F_ASSIGN or F_ASSIGN_AND_POP ) */ case F_LTOSVAL_CALL_BUILTIN_AND_ASSIGN_POP: case F_LTOSVAL_CALL_BUILTIN_AND_ASSIGN: return; #endif case F_CALL_BUILTIN_AND_POP: ins_f_byte_with_arg( F_CALL_BUILTIN, b ); ins_f_byte( F_POP_VALUE ); return; case F_MARK_CALL_BUILTIN_AND_RETURN: ins_f_byte_with_arg( F_MARK_CALL_BUILTIN, b ); ins_f_byte( F_DUMB_RETURN ); return; case F_MARK_CALL_BUILTIN_AND_POP: ins_f_byte_with_arg( F_MARK_CALL_BUILTIN, b ); ins_f_byte( F_POP_VALUE ); return; case F_CALL_BUILTIN1_AND_POP: ins_f_byte_with_arg( F_CALL_BUILTIN1, b ); ins_f_byte( F_POP_VALUE ); return; case F_CALL_BUILTIN_AND_RETURN: ins_f_byte_with_arg( F_CALL_BUILTIN, b ); ins_f_byte( F_DUMB_RETURN ); return; case F_CALL_BUILTIN: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_mark_sp_reg(); amd64_load_sp_reg(); mov_mem_reg( mark_sp_reg, -sizeof(struct svalue*), P_REG_RAX ); amd64_add_mark_sp( -1 ); mov_reg_reg( sp_reg, ARG1_REG ); sub_reg_reg( ARG1_REG, P_REG_RAX ); shr_reg_imm( ARG1_REG, 4 ); /* arg1 = (sp_reg - *--mark_sp)/16 (sizeof(svalue)) */ /* FALL_THROUGH */ case F_MARK_CALL_BUILTIN: if(a == F_MARK_CALL_BUILTIN ) { ins_debug_instr_prologue(a-F_OFFSET, b, 0); mov_imm_reg( 0, ARG1_REG ); } /* FALL_THROUGH */ case F_CALL_BUILTIN1: if(a == F_CALL_BUILTIN1 ) { ins_debug_instr_prologue(a-F_OFFSET, b, 0); mov_imm_reg( 1, ARG1_REG ); } /* Note: It is not actually possible to do ins_debug_instr_prologue * here. */ amd64_call_c_opcode(Pike_compiler->new_program->constants[b].sval.u.efun->function, I_UPDATE_SP); return; case F_CONSTANT: { struct svalue *cval = &Pike_compiler->new_program->constants[b].sval; ins_debug_instr_prologue(a-F_OFFSET, b, 0); if( TYPEOF(*cval) == PIKE_T_INT && SUBTYPEOF(*cval) == NUMBER_UNDEFINED) { amd64_load_fp_reg(); amd64_load_sp_reg(); /* We end up here in programs decoded from decode_value. constants are not restored until after the program code is generated. (there is no way to differentiate a 'real' undefined here) */ mov_mem_reg( fp_reg, OFFSETOF(pike_frame,context), P_REG_RCX ); mov_mem_reg( P_REG_RCX, OFFSETOF(inherit,prog), P_REG_RCX ); mov_mem_reg( P_REG_RCX, OFFSETOF(program,constants), P_REG_RCX ); add_reg_imm( P_REG_RCX, b*sizeof(struct program_constant) + OFFSETOF(program_constant,sval) ); amd64_push_svaluep( P_REG_RCX ); /* ~14 instructions total, 3-4 deref */ } else { amd64_load_sp_reg(); mov_imm_mem(cval->tu.type_subtype, sp_reg, SVAL(0).type); if( TYPEOF(*cval) >= MIN_REF_TYPE ) { mov_imm_reg(cval->u.integer, P_REG_RCX); mov_reg_mem(P_REG_RCX, sp_reg, SVAL(0).value); add_imm_mem( 1, P_REG_RCX, OFFSETOF(pike_string, refs)); } else { mov_imm_mem(cval->u.integer, sp_reg, SVAL(0).value); } amd64_add_sp(1); /* 2 or 4 instructions total, 0-1 deref */ } } return; case F_GLOBAL_LVALUE: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); amd64_load_sp_reg(); amd64_push_this_object( ); mov_imm_mem( T_OBJ_INDEX, sp_reg, OFFSETOF(svalue, tu.t.type)); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, context), P_REG_RAX); mov_mem16_reg( P_REG_RAX,OFFSETOF(inherit, identifier_level), P_REG_RAX); add_reg_imm( P_REG_RAX, b ); mov_reg_mem( P_REG_RAX, sp_reg, OFFSETOF(svalue,u.identifier) ); amd64_add_sp( 1 ); return; case F_LOCAL_LVALUE: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); amd64_load_sp_reg(); /* &frame->locals[b] */ mov_mem_reg( fp_reg, OFFSETOF(pike_frame, locals), P_REG_RAX); add_reg_imm( P_REG_RAX, b*sizeof(struct svalue)); mov_imm_mem( T_SVALUE_PTR, sp_reg, OFFSETOF(svalue, tu.t.type)); mov_reg_mem( P_REG_RAX, sp_reg, OFFSETOF(svalue,u.lval) ); mov_imm_mem( T_VOID, sp_reg, OFFSETOF(svalue, tu.t.type)+sizeof(struct svalue)); amd64_add_sp( 2 ); return; case F_PROTECT_STACK: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); mov_imm_mem16(b, fp_reg, OFFSETOF(pike_frame, expendible_offset)); return; case F_MARK_AT: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); amd64_load_mark_sp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, locals), ARG1_REG); if (b) { add_reg_imm_reg(ARG1_REG, sizeof(struct svalue) * b, ARG1_REG); } mov_reg_mem(ARG1_REG, mark_sp_reg, 0x00); amd64_add_mark_sp( 1 ); return; } update_arg1(b); ins_f_byte(a); } int amd64_ins_f_jump_with_arg(unsigned int op, INT32 a, int backward_jump) { LABELS(); if (!(instrs[op - F_OFFSET].flags & I_BRANCH)) return -1; switch( op ) { /* case F_BRANCH_IF_TYPE_IS_NOT: */ /* ins_debug_instr_prologue(op-F_OFFSET, a, 0); */ /* amd64_load_sp_reg(); */ /* amd64_add_sp(-1); */ /* mov_sval_type( sp_reg, P_REG_RAX ); */ /* cmp_reg32_imm(P_REG_RAX, PIKE_T_OBJECT ); */ /* jne( &label_A ); */ /* amd64_add_sp(1); */ /* amd64_call_c_opcode(instrs[op-F_OFFSET].address, I_UPDATE_SP); */ /* jz( &label_B ); /\* do not branch. *\/ */ /* /\* branch. *\/ */ /* mov_imm_reg( a, P_REG_RAX ); */ /* jmp( &label_C ); */ /* amd64_load_sp_reg(); */ /* label_A; */ /* amd64_free_svalue( sp_reg, 0); */ /* label_C; */ /* cmp_reg32_imm(P_REG_RAX, a); */ /* int res= jnz_imm_rel32(0); */ /* label_B; */ /* return res; */ case F_BRANCH_IF_NOT_LOCAL: case F_BRANCH_IF_LOCAL: ins_debug_instr_prologue(op-F_OFFSET, a, 0); amd64_load_fp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame, locals), ARG1_REG); add_reg_imm( ARG1_REG, a*sizeof(struct svalue)); /* if( type == PIKE_T_INT ) u.integer -> RAX else if( type == PIKE_T_OBJECT || type == PIKE_T_FUNCTION ) call svalue_is_true(&local) else 1 -> RAX The tests are ordered assuming integers are most commonly checked. That is not nessasarily true. */ mov_sval_type( ARG1_REG, P_REG_RCX ); cmp_reg32_imm( P_REG_RCX, PIKE_T_INT ); je( &label_C ); mov_imm_reg( 1, P_REG_RAX ); shl_reg32_reg( P_REG_RAX, P_REG_RCX ); and_reg32_imm( P_REG_RAX, BIT_FUNCTION|BIT_OBJECT ); jnz( &label_A ); /* Not object, int or function. Always true. */ mov_imm_reg( 1, P_REG_RAX ); jmp( &label_B ); LABEL_A; amd64_call_c_function(svalue_is_true); jmp( &label_B ); LABEL_C; mov_mem_reg( ARG1_REG, OFFSETOF(svalue, u.integer ), P_REG_RAX ); /* integer. */ LABEL_B; test_reg( P_REG_RAX ); if( op == F_BRANCH_IF_LOCAL ) return jnz_imm_rel32(0); return jz_imm_rel32(0); } maybe_update_pc(); update_arg1(a); return amd64_ins_f_jump(op, backward_jump); } void ins_f_byte_with_2_args(unsigned int a, INT32 b, INT32 c) { maybe_update_pc(); switch(a) { case F_NUMBER64: ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_push_int((((UINT64)b)<<32)|(unsigned INT32)c, 0); return; case F_MARK_AND_EXTERNAL: ins_f_byte(F_MARK); ins_f_byte_with_2_args(F_EXTERNAL, b, c); return; case F_CLEAR_N_LOCAL: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_fp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, locals), P_REG_RBX); add_reg_imm(P_REG_RBX, b*sizeof(struct svalue)); if( c > 1 ) add_reg_imm_reg(P_REG_RBX, c*sizeof(struct svalue), P_REG_RBP ); LABEL_A; amd64_free_svalue(P_REG_RBX, 0); mov_imm_mem(PIKE_T_INT, P_REG_RBX, OFFSETOF(svalue, tu.t.type)); mov_imm_mem(0, P_REG_RBX, OFFSETOF(svalue, u.integer)); if( c > 1 ) { add_reg_imm(P_REG_RBX, sizeof(struct svalue ) ); cmp_reg_reg( P_REG_RBX, P_REG_RBP ); jne(&label_A); } } return; case F_LOCAL_LOCAL_INDEX: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_fp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame,locals), P_REG_RDX); add_reg_imm_reg( P_REG_RDX, b*sizeof(struct svalue), P_REG_RBX); add_reg_imm_reg( P_REG_RDX, c*sizeof(struct svalue), P_REG_RCX); /* bx = svalue for value */ /* cx = svalue for index */ mov_sval_type( P_REG_RBX, P_REG_RAX ); mov_sval_type( P_REG_RCX, P_REG_RDX ); shl_reg_imm( P_REG_RAX, 8 ); /* fixme: Add add_mem8_reg */ add_reg_reg( P_REG_RAX, P_REG_RDX ); cmp_reg32_imm( P_REG_RAX, (PIKE_T_ARRAY<<8)|PIKE_T_INT ); jne( &label_B ); /* ax = value->tyupe<<8|index->type */ mov_mem_reg( P_REG_RBX, 8, P_REG_RBX ); /* value */ mov_mem_reg( P_REG_RCX, 8, P_REG_R9 ); /* int */ /* dx = value->u.array, bx = index */ /* Array and int index. */ mov_mem32_reg( P_REG_RDX, OFFSETOF(array,size), P_REG_R8 ); cmp_reg32_imm( P_REG_RBX, 0 ); jge( &label_D ); /* index less than 0, add array size */ add_reg_reg( P_REG_RBX, P_REG_R8 ); LABEL_D; cmp_reg32_imm( P_REG_RBX, 0 ); jl( &label_B ); // index (still) <0 cmp_reg_reg( P_REG_RBX, P_REG_R8); jge( &label_B ); //index >=size /* array->item + x to stack. done */ mov_mem_reg( P_REG_RDX, OFFSETOF(array,item), P_REG_RCX ); /* cx = arr->item */ shl_reg_imm( P_REG_RBX, 4 ); add_reg_reg( P_REG_RBX, P_REG_RCX ); /* bx = bx * sizeof(svalue) + cx */ amd64_push_svaluep( P_REG_RBX ); jmp( &label_C ); LABEL_B; /* something else. */ update_arg1(b); update_arg2(c); amd64_call_c_opcode(instrs[a-F_OFFSET].address, instrs[a-F_OFFSET].flags); LABEL_C; /* done */ } return; case F_PRIVATE_IF_DIRECT_GLOBAL: { LABELS(); amd64_load_sp_reg(); ins_debug_instr_prologue(a-F_OFFSET, b, c); /* do not assign if this object is destructed. */ mov_mem_reg( fp_reg, OFFSETOF(pike_frame,current_object), ARG2_REG ); mov_mem_reg( fp_reg, OFFSETOF(pike_frame,context), ARG3_REG ); /* if ctx->prog != arg1->prog */ mov_mem_reg( ARG3_REG, OFFSETOF(inherit,prog), P_REG_R8 ); mov_mem_reg( ARG2_REG, OFFSETOF(object,prog), P_REG_RAX ); cmp_reg_reg(P_REG_R8,P_REG_RAX); je(&label_A); mov_reg_reg(sp_reg, ARG1_REG); mov_mem16_reg(ARG3_REG, OFFSETOF(inherit, identifier_level), ARG3_REG); add_reg_imm(ARG3_REG, c); amd64_call_c_function(low_object_index_no_free); amd64_add_sp(1); jmp(&label_B); LABEL_A; mov_mem_reg(ARG2_REG, OFFSETOF(object,storage), P_REG_RBX ); add_reg_mem(P_REG_RBX, ARG3_REG, OFFSETOF(inherit,storage_offset)); add_reg_imm(P_REG_RBX, b ); amd64_push_svaluep( P_REG_RBX ); LABEL_B; return; } case F_ASSIGN_PRIVATE_IF_DIRECT_GLOBAL: { LABELS(); amd64_load_sp_reg(); ins_debug_instr_prologue(a-F_OFFSET, b, c); /* do not assign if this object is destructed. */ mov_mem_reg( fp_reg, OFFSETOF(pike_frame,current_object), ARG1_REG ); mov_mem_reg( fp_reg, OFFSETOF(pike_frame,context), ARG2_REG ); /* if ctx->prog != arg1->prog */ mov_mem_reg( ARG1_REG, OFFSETOF(object,prog), P_REG_RAX ); mov_mem_reg( ARG2_REG, OFFSETOF(inherit,prog), P_REG_R8 ); cmp_reg_reg(P_REG_R8,P_REG_RAX); je(&label_A); /* arg1 = object */ /* arg2 = c + identifier_level */ /* arg3 = Pike_sp-1 */ mov_mem16_reg( ARG2_REG, OFFSETOF(inherit,identifier_level), ARG2_REG); add_reg_imm( ARG2_REG, c ); add_reg_imm_reg( sp_reg, -1*sizeof(struct svalue), ARG3_REG ); amd64_call_c_function(object_low_set_index); jmp(&label_B); LABEL_A; mov_mem_reg(ARG1_REG, OFFSETOF(object,storage), P_REG_RBX ); add_reg_mem(P_REG_RBX, ARG2_REG, OFFSETOF(inherit,storage_offset)); add_reg_imm(P_REG_RBX, b ); amd64_free_svalue( P_REG_RBX, 0 ); amd64_assign_svalue_no_free( P_REG_RBX, sp_reg, -sizeof(struct svalue)); amd64_ref_svalue(P_REG_RBX,0); LABEL_B; } return; case F_ASSIGN_PRIVATE_TYPED_GLOBAL_AND_POP: case F_ASSIGN_PRIVATE_TYPED_GLOBAL: { LABELS(); amd64_load_sp_reg(); ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_get_storage( P_REG_RBX, b ); /* do not assign anything if this object is destructed. */ /* we really only need to redo this check after we have called some other function. It is sort of hard to know when that happens while generating the code, however. Simply assigning the global could in theory actually destruct this object (old value includes something with a destroy that calls destruct on this object...) Note that nothing crash if we do the assign. We "just" leak the variable when the storage is eventually free:d. The generated code does look sort of silly, however. */ mov_mem_reg( fp_reg, OFFSETOF(pike_frame,current_object), ARG1_REG ); mov_mem_reg( ARG1_REG, OFFSETOF(object,prog), P_REG_RAX ); test_reg(P_REG_RAX); jnz(&label_A); /* will not return. */ amd64_call_c_function(object_low_set_index); LABEL_A; /* 1: check type of argument */ mov_mem8_reg( sp_reg, -sizeof(struct svalue )+OFFSETOF(svalue,tu.t.type), P_REG_RAX); cmp_reg32_imm( P_REG_RAX, c ); je( &label_B ); /* not the same type. Fall back to use C-function (for code size mainly).. */ mov_reg_reg( P_REG_RBX, ARG1_REG ); mov_imm_reg( c, ARG2_REG ); add_reg_imm_reg( sp_reg, -sizeof(struct svalue), ARG3_REG ); amd64_call_c_function(assign_to_short_svalue); /* pop stack if needed. */ if( a == F_ASSIGN_PRIVATE_TYPED_GLOBAL_AND_POP ) { amd64_add_sp(-1); /* this will either have assigned 0 or thrown an error. * if we assigned 0, it was because the argument evaluated as false. * However, that means that we might possibly have to free it here.. * * We do not even know that is has at least two references. */ amd64_free_svalue( sp_reg, 0 ); } jmp( &label_E ); /* pop or not. */ LABEL_B; /* at this point: o->storage + off in RBX. */ if( c >= MIN_REF_TYPE ) { mov_mem_reg( P_REG_RBX, 0, P_REG_RAX ); test_reg(P_REG_RAX); /* old value == NULL? */ jz(&label_C); /* deref. */ add_mem32_imm( P_REG_RAX, OFFSETOF(pike_string,refs), -1); jnz(&label_C); mov_reg_reg( P_REG_RBX, ARG1_REG ); mov_imm_reg( c, ARG2_REG ); amd64_call_c_function(really_free_short_svalue_ptr); } LABEL_C; /* old value is gone. Assign new value */ mov_mem_reg( sp_reg, -8, P_REG_RAX ); mov_reg_mem( P_REG_RAX, P_REG_RBX, 0 ); if( a == F_ASSIGN_PRIVATE_TYPED_GLOBAL_AND_POP ) amd64_add_sp( -1 ); else if( c >= MIN_REF_TYPE ) add_mem_imm( P_REG_RAX, OFFSETOF(pike_string,refs), 1 ); LABEL_E; } return; case F_PRIVATE_TYPED_GLOBAL: /* b -> off, c -> type */ ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_sp_reg(); if( c < MIN_REF_TYPE ) { /* really: int or float. And right now, only float */ amd64_get_storage( P_REG_RBX, b ); mov_mem_reg( P_REG_RBX, 0, P_REG_RBX ); mov_imm_mem( c, sp_reg, 0 ); mov_reg_mem( P_REG_RBX, sp_reg, 8 ); amd64_add_sp(1); } else { LABELS(); /* one of the refcounted types. */ amd64_get_storage( P_REG_RBX, b ); mov_mem_reg( P_REG_RBX, 0, P_REG_RBX ); test_reg( P_REG_RBX ); jnz(&label_A); amd64_push_int(0,1); jmp(&label_B); LABEL_A; add_mem_imm( P_REG_RBX, 0, 1 ); mov_imm_mem( c, sp_reg, 0 ); mov_reg_mem( P_REG_RBX, sp_reg, 8 ); amd64_add_sp(1); LABEL_B; } return; case F_ADD_LOCAL_INT: case F_ADD_LOCAL_INT_AND_POP: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_fp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame, locals), ARG1_REG); add_reg_imm( ARG1_REG, b*sizeof(struct svalue) ); /* arg1 = dst arg2 = int */ mov_sval_type( ARG1_REG, P_REG_RAX ); cmp_reg32_imm( P_REG_RAX, PIKE_T_INT ); jne(&label_A); /* Fallback */ mov_imm_mem( PIKE_T_INT, ARG1_REG, OFFSETOF(svalue, tu.t.type)); add_imm_mem( c, ARG1_REG,OFFSETOF(svalue,u.integer)); jno( &label_B); add_imm_mem( -c, ARG1_REG,OFFSETOF(svalue,u.integer)); /* Overflow. Use C version */ LABEL_A; update_arg2(c); update_arg1(b); ins_f_byte(a); /* Push already done by C version. */ if( a == F_ADD_LOCAL_INT ) jmp( &label_C ); LABEL_B; if( a == F_ADD_LOCAL_INT ) { /* push the local. */ /* We know it's an integer (since we did not use the fallback) */ amd64_load_sp_reg(); mov_mem_reg( ARG1_REG, OFFSETOF(svalue,u.integer), P_REG_RAX ); amd64_push_int_reg( P_REG_RAX ); } LABEL_C; return; } #if 0 /* this is a: nonworking, and b: not really all that more efficient anyway.. */ case F_APPLY_N: ins_debug_instr_prologue(a-F_OFFSET, b, c); mov_imm_reg( APPLY_SVALUE_STRICT, ARG1_REG ); mov_imm_reg( c, ARG2_REG ); mov_ptr_reg( &((Pike_fp->context->prog->constants + b)->sval), ARG3_REG ); clear_reg( ARG4_REG ); amd64_call_c_opcode(mega_apply, I_UPDATE_SP); return; #endif case F_CALL_BUILTIN_N: ins_debug_instr_prologue(a-F_OFFSET, b, c); mov_imm_reg( c, ARG1_REG ); amd64_call_c_opcode(Pike_compiler->new_program->constants[b].sval.u.efun->function, I_UPDATE_SP); return; case F_ADD_LOCALS_AND_POP: { LABELS(); ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame, locals), ARG1_REG); add_reg_imm( ARG1_REG, b*sizeof(struct svalue) ); add_reg_imm_reg( ARG1_REG,(c-b)*sizeof(struct svalue), ARG2_REG ); /* arg1 = dst arg2 = src */ mov_sval_type( ARG1_REG, P_REG_RAX ); mov_sval_type( ARG2_REG, P_REG_RBX ); shl_reg_imm( P_REG_RAX, 8 ); add_reg_reg( P_REG_RAX, P_REG_RBX ); cmp_reg32_imm( P_REG_RAX, (PIKE_T_INT<<8) | PIKE_T_INT ); jne(&label_A); /* Fallback */ mov_mem_reg( ARG2_REG, OFFSETOF(svalue,u.integer), P_REG_RAX ); add_reg_mem( P_REG_RAX, ARG1_REG, OFFSETOF(svalue,u.integer)); jo( &label_A); /* Clear subtype */ mov_imm_mem( PIKE_T_INT, ARG1_REG,OFFSETOF(svalue, tu.t.type)); mov_reg_mem( P_REG_RAX, ARG1_REG, OFFSETOF(svalue,u.integer)); jmp( &label_B ); LABEL_A; update_arg2(c); update_arg1(b); ins_f_byte(a); /* Will call C version */ LABEL_B; return; } case F_ASSIGN_LOCAL_NUMBER_AND_POP: ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_fp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame, locals), ARG1_REG); add_reg_imm( ARG1_REG,b*sizeof(struct svalue) ); mov_reg_reg( ARG1_REG, P_REG_RBX ); amd64_free_svalue(ARG1_REG, 0); mov_imm_mem(c, P_REG_RBX, OFFSETOF(svalue, u.integer)); mov_imm_mem32(PIKE_T_INT, P_REG_RBX, OFFSETOF(svalue, tu.t.type)); return; case F_LOCAL_2_GLOBAL: ins_debug_instr_prologue(a-F_OFFSET, b, 0); amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame, locals), ARG3_REG ); add_reg_imm( ARG3_REG, c*sizeof(struct svalue) ); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, current_object), ARG1_REG); mov_mem_reg(fp_reg, OFFSETOF(pike_frame,context), ARG2_REG); mov_mem16_reg(ARG2_REG, OFFSETOF(inherit, identifier_level), ARG2_REG); add_reg_imm( ARG2_REG, b ); amd64_call_c_function( object_low_set_index ); return; case F_LEXICAL_LOCAL: if( c < 5 ) { ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_fp_reg(); mov_reg_reg( fp_reg, P_REG_RAX ); while(c--) mov_mem_reg( P_REG_RAX, OFFSETOF(pike_frame,scope), P_REG_RAX ); mov_mem_reg( P_REG_RAX, OFFSETOF(pike_frame,locals), P_REG_RAX ); add_reg_imm_reg( P_REG_RAX, b*sizeof(struct svalue), P_REG_RBX ); amd64_push_svaluep( P_REG_RBX ); return; } /* use c version. Could have a loop version here. */ break; case F_LEXICAL_LOCAL_LVALUE: if( c < 5 ) { ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_fp_reg(); amd64_load_sp_reg(); mov_reg_reg( fp_reg, P_REG_RAX ); while(c--) mov_mem_reg( P_REG_RAX, OFFSETOF(pike_frame,scope), P_REG_RAX ); mov_mem_reg( P_REG_RAX, OFFSETOF(pike_frame,locals), P_REG_RAX ); add_reg_imm_reg( P_REG_RAX, b*sizeof(struct svalue), P_REG_RAX ); mov_imm_mem( T_SVALUE_PTR, sp_reg, OFFSETOF(svalue, tu.t.type)); mov_reg_mem( P_REG_RAX, sp_reg, OFFSETOF(svalue,u.lval) ); mov_imm_mem( T_VOID, sp_reg, OFFSETOF(svalue, tu.t.type)+sizeof(struct svalue)); amd64_add_sp( 2 ); return; } /* use c version. Could have a loop version here. */ break; case F_LOCAL_2_LOCAL: ins_debug_instr_prologue(a-F_OFFSET, b, c); if( b != c ) { amd64_load_fp_reg(); mov_mem_reg( fp_reg, OFFSETOF(pike_frame, locals), P_REG_RBX ); add_reg_imm( P_REG_RBX, b*sizeof(struct svalue) ); /* RBX points to dst. */ amd64_free_svalue( P_REG_RBX, 0 ); /* assign rbx[0] = rbx[c-b] */ mov_mem_reg( P_REG_RBX, (c-b)*sizeof(struct svalue), P_REG_RAX ); mov_mem_reg( P_REG_RBX, (c-b)*sizeof(struct svalue)+8, P_REG_RCX ); mov_reg_mem( P_REG_RAX, P_REG_RBX, 0 ); mov_reg_mem( P_REG_RCX, P_REG_RBX, 8 ); amd64_ref_svalue( P_REG_RBX, 1 ); } return; case F_2_LOCALS: #if 1 ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, locals), P_REG_R8); add_reg_imm( P_REG_R8, b*sizeof(struct svalue) ); amd64_push_svaluep(P_REG_R8); add_reg_imm( P_REG_R8, (c-b)*sizeof(struct svalue) ); amd64_push_svaluep(P_REG_R8); #else ins_f_byte_with_arg( F_LOCAL, b ); ins_f_byte_with_arg( F_LOCAL, c ); #endif return; case F_FILL_STACK: { LABELS(); if (!b) return; ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_fp_reg(); amd64_load_sp_reg(); mov_mem_reg(fp_reg, OFFSETOF(pike_frame, locals), ARG1_REG); add_reg_imm(ARG1_REG, b*sizeof(struct svalue)); jmp(&label_A); LABEL_B; amd64_push_int(0, c); LABEL_A; cmp_reg_reg(sp_reg, ARG1_REG); jl(&label_B); } return; case F_INIT_FRAME: ins_debug_instr_prologue(a-F_OFFSET, b, c); amd64_load_fp_reg(); if(OFFSETOF(pike_frame, num_locals) != OFFSETOF(pike_frame, num_args)-2 ) Pike_fatal("This code does not with unless num_args\n" "directly follows num_locals in struct pike_frame\n"); mov_imm_mem32( (b<<16)|c, fp_reg, OFFSETOF(pike_frame, num_locals)); return; } update_arg2(c); update_arg1(b); ins_f_byte(a); } int amd64_ins_f_jump_with_2_args(unsigned int op, INT32 a, INT32 b, int backward_jump) { if (!(instrs[op - F_OFFSET].flags & I_BRANCH)) return -1; maybe_update_pc(); update_arg2(b); update_arg1(a); return amd64_ins_f_jump(op, backward_jump); } void amd64_update_f_jump(INT32 offset, INT32 to_offset) { upd_pointer(offset, to_offset - offset - 4); } INT32 amd64_read_f_jump(INT32 offset) { return read_pointer(offset) + offset + 4; } #define OP_PREFIX 0x10000000UL #define G1 (OP_PREFIX|0) #define G2 (OP_PREFIX|1) #define G3 (OP_PREFIX|2) #define G4 (OP_PREFIX|3) /* Table switch */ #define OP_MULTIBYTE 0x20000000UL #define OP_F (OP_MULTIBYTE|0) #define OP_F_38 (OP_MULTIBYTE|1) #define OP_F_3A (OP_MULTIBYTE|2) /* Additional fields */ #define OP_RM 0x00010000 /* ModR/M */ #define OP_DISPL 0x00020000 /* Displacement */ #define OP_IMM 0x00040000 /* Immediate */ #define OP_PCREL 0x00080000 /* PC-relative */ /* Implicit arguments */ #define OP_REG 0x00100000 /* Register in low 3 bits. */ #define OP_IMPLICIT_A 0x00200000 #define OP_IMPLICIT_C 0x00800000 #define OP_REG_S 0x00400000 /* Argument ordering */ #define OP_B_RM 0x00008000 /* B arg before RM arg. */ /* Operand widths */ #define OP_8 0x01000000 /* 8-bit */ #define OP_S8 0x02000000 /* 8-bit sign extended to 16 */ /* ModRM lookup */ #define OP_OPS 0x40000000 /* Lookup in modrm_ops */ #define OP_S 0 #define REG (OP_REG) #define RRM8 (OP_8|OP_RM|OP_B_RM) #define RMR8 (OP_8|OP_RM) #define RMR (OP_RM) #define RRM (OP_RM|OP_B_RM) #define RRMI8 (OP_8|OP_RM|OP_B_RM|OP_IMM) #define RRMI (OP_RM|OP_B_RM|OP_IMM) #define SRM (OP_S|OP_RM|OP_B_RM) #define RMS (OP_S|OP_RM) #define ALM8 (OP_8|OP_IMPLICIT_A|OP_RM|OP_B_RM) #define AM (OP_IMPLICIT_A|OP_RM|OP_B_RM) #define MAL8 (OP_IMPLICIT_A|OP_RM|OP_8) #define MA (OP_IMPLICIT_A|OP_RM) #define RI8 (OP_RM|OP_IMM|OP_8) #define RI (OP_RM|OP_IMM) #define RMI8OP (OP_RM|OP_IMM|OP_8|OP_OPS) #define RMSI8OP (OP_RM|OP_IMM|OP_S8|OP_OPS) #define RMIOP (OP_RM|OP_IMM|OP_OPS) #define ALI8 (OP_IMPLICIT_A|OP_IMM|OP_8) #define AI (OP_IMPLICIT_A|OP_IMM) #define RM8OP (OP_RM|OP_8|OP_OPS) #define RMOP (OP_RM|OP_OPS) #define RMC8OP (OP_RM|OP_8|OP_OPS|OP_IMPLICIT_C) #define RMCOP (OP_RM|OP_OPS|OP_IMPLICIT_C) #define PCREL (OP_PCREL) #define PCREL8 (OP_PCREL|OP_8) #define RM (OP_RM) static const char *modrm_ops[6][8] = { /* #0: ALU operations (Opcodes 0x80, 0x81, 0x83). */ { "add", "or", "adc", NULL, "and", "sub", NULL, "cmp", }, /* #1: Shift operations */ { NULL, NULL, NULL, NULL, "sal", "shr", NULL, "sar", }, /* #2: More ALU operations (Opcodes 0xf6, 0xf7). */ { "test", NULL, NULL, "neg", "imul", NULL, NULL, "idiv", }, /* #3: Inc/dec (Opcode 0xff) */ { "inc", "dec", "call", "call", "jmp", "jmp", NULL, NULL, }, /* #4: Mov (Opcodes 0xc6, 0xc7). */ { "mov", NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, /* #5: Bit tests (Opcode 0xba) */ { NULL, NULL, NULL, NULL, "bt", "bts", "btr", "btc", }, }; struct amd64_opcode { const char *name; unsigned INT64 flags; }; static struct amd64_opcode amd64_opcodes[4][256] = { /* Main table. */ { /* 0x00 */ { "add", RMR8, }, { "add", RMR, }, { "add", RRM8, }, { "add", RRM, }, { "add", ALI8, }, { "add", AI, }, { NULL, 0, }, { NULL, 0, }, { "or", RMR8, }, { "or", RMR, }, { "or", RRM8, }, { "or", RRM, }, { "or", ALI8, }, { "or", AI, }, { NULL, 0, }, { "F", OP_F, }, /* 0x10 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x20 */ { "and", RMR8, }, { "and", RMR, }, { "and", RRM8, }, { "and", RRM, }, { "and", ALI8, }, { "and", AI, }, { "es", G2, }, { NULL, 0, }, { "sub", RMR8, }, { "sub", RMR, }, { "sub", RRM8, }, { "sub", RRM, }, { "sub", ALI8, }, { "sub", AI, }, { "cs", G2, }, { NULL, 0, }, /* 0x30 */ { "xor", RMR8, }, { "xor", RMR, }, { "xor", RRM8, }, { "xor", RRM, }, { NULL, 0, }, { NULL, 0, }, { "ss", G2, }, { NULL, 0, }, { "cmp", RMR8, }, { "cmp", RMR, }, { "cmp", RRM8, }, { "cmp", RRM, }, { "cmp", ALI8, }, { "cmp", AI, }, { "ds", G2, }, { NULL, 0, }, /* 0x40 - REX */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x50 */ { "push", REG, }, { "push", REG, }, { "push", REG, }, { "push", REG, }, { "push", REG, }, { "push", REG, }, { "push", REG, }, { "push", REG, }, { "pop", REG, }, { "pop", REG, }, { "pop", REG, }, { "pop", REG, }, { "pop", REG, }, { "pop", REG, }, { "pop", REG, }, { "pop", REG, }, /* 0x60 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "fs", G2, }, { "gs", G2, }, { "osize", G3, }, { "asize", G4, }, { NULL, 0, }, { "imul", RRMI, }, { NULL, 0, }, { "imul", RRMI8, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x70 */ { "jo", PCREL8, }, { "jno", PCREL8, }, { "jb", PCREL8, }, { "jae", PCREL8, }, { "jz", PCREL8, }, { "jnz", PCREL8, }, { "jbe", PCREL8, }, { "ja", PCREL8, }, { "js", PCREL8, }, { "jns", PCREL8, }, { "jp", PCREL8, }, { "jpo", PCREL8, }, { "jnge", PCREL8, }, { "jge", PCREL8, }, { "jle", PCREL8, }, { "jg", PCREL8, }, /* 0x80 */ { "and", RMI8OP, }, { "and", RMIOP, }, { NULL, 0, }, { "and", RMSI8OP, }, { "test", RMR8, }, { "test", RMR, }, { NULL, 0, }, { NULL, 0, }, { "mov", RMR8, }, { "mov", RMR, }, { "mov", RRM8, }, { "mov", RRM, }, { "mov", RMS, }, { "lea", RRM, }, { "mov", SRM, }, { NULL, 0, }, /* 0x90 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xa0 */ { "mov", ALM8, }, { "mov", AM, }, { "mov", MAL8, }, { "mov", MA, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "test", ALI8, }, { "test", AI, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xb0 */ { "mov", RI8, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "mov", RI, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xc0 */ { "sal", RMI8OP|1, }, { "sal", RMIOP|1, }, { NULL, 0, }, { "ret", 0, }, { NULL, 0, }, { NULL, 0, }, { "mov", RMI8OP|4, }, { "mov", RMIOP|4, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xd0 */ { "sal", RM8OP|1, }, { "sal", RMOP|1, }, { "sal", RMC8OP|1, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "jmp", PCREL, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "jmp", PCREL8, }, { NULL, 0, }, /* 0xe0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "jcxz", PCREL8, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "call", PCREL, }, { NULL, 0, }, { NULL, 0, }, { "jmp", PCREL8, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xf0 */ { "lock", G1, }, { NULL, 0, }, { "repne", G1, }, { "rep", G1, }, { NULL, 0, }, { "cmc", 0, }, { "neg", RM8OP|2, }, { "neg", RMOP|2, }, { "clc", 0, }, { NULL, 0, }, { "cli", 0, }, { NULL, 0, }, { "cld", 0, }, { NULL, 0, }, { "dec", RM8OP|3, }, { "dec", RMOP|3, }, }, /* Opcode prefix 0x0f. */ { /* 0x00 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x10 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x20 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x30 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "aes|blendvps/d|crc32", OP_F_38, }, { NULL, 0, }, { "aes|blendps/d", OP_F_3A, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x40 */ { "cmovo", RRM, }, { "cmovno", RRM, }, { "cmovb", RRM, }, { "cmovae", RRM, }, { "cmove", RRM, }, { "cmovne", RRM, }, { "cmovbe", RRM, }, { "cmova", RRM, }, { "cmovs", RRM, }, { "cmovns", RRM, }, { "cmovp", RRM, }, { "cmovnp", RRM, }, { "cmovel", RRM, }, { "cmovge", RRM, }, { "cmovle", RRM, }, { "cmovg", RRM, }, /* 0x50 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x60 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "movdqa", RRM, }, /* 0x70 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "movdqa", RMR, }, /* 0x80 */ { "jo", PCREL, }, { "jno", PCREL, }, { "jb", PCREL, }, { "jae", PCREL, }, { "je", PCREL, }, { "jne", PCREL, }, { "jbe", PCREL, }, { "ja", PCREL, }, { "js", PCREL, }, { "jns", PCREL, }, { "jp", PCREL, }, { "jnp", PCREL, }, { "jl", PCREL, }, { "jge", PCREL, }, { "jle", PCREL, }, { "jg", PCREL, }, /* 0x90 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "eq", RM, }, { "neq", RM, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "lt", RM, }, { "gte", RM, }, { "lte", RM, }, { "gt", RM, }, /* 0xa0 */ { NULL, 0, }, { NULL, 0, }, { "cpuid", 0, }, { "bt", RMR, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "bts", RMR, }, { NULL, 0, }, { NULL, 0, }, { "clflush", RM, }, { "imul", RRM, }, /* 0xb0 */ { "cmpxchg", RMR8, }, { "cmpxchg", RMR, }, { NULL, 0, }, { "btr", RMR, }, { NULL, 0, }, { NULL, 0, }, { "movzx", RRM, }, { "movzx", RRM, }, { "bsf", RRM, }, { "bsr", RRM, }, { "bt", RMIOP|5, }, { "btc", RMR, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xc0 */ { NULL, 0, }, { NULL, 0, }, { "cmpp/ss/d", RRMI8, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "cmpxchg8b", RM, }, { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, /* 0xd0 */ { "addsubps/d", RRM, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xe0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xf0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, }, /* Opcode prefix 0x0f 0x38: AES, BLENDVP, CRC32. */ { /* 0x00 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x10 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "blendvps", RRM, }, { "blendvpd", RRM, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x20 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x30 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x40 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x50 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x60 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x70 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x80 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x90 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xa0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xb0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xc0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xd0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "aesimc", RRM, }, { "aesenc", RRM, }, { "aesenclast", RRM, }, { "aesdec", RRM, }, { "aesdeclast", RRM, }, /* 0xe0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xf0 */ { "crc32", RRM8, }, { "crc32", RRM, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, }, /* Opcode prefix 0x0f 0x3a: AES, BLENDP. */ { /* 0x00 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "blendps", RRMI8, }, { "blendpd", RRMI8, }, { NULL, 0, }, { NULL, 0, }, /* 0x10 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x20 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x30 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x40 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x50 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x60 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x70 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x80 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0x90 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xa0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xb0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xc0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xd0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "aeskeygenassist", RRMI8, }, /* 0xe0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, /* 0xf0 */ { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, }, }; const char *amd64_registers[16] = { "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", }; const char *amd64_describe_reg(int rex, int reg) { if (rex) reg += 8; return amd64_registers[reg]; } size_t amd64_readint32(PIKE_OPCODE_T *pc, char *buf) { unsigned INT32 val = ((unsigned INT32 *)pc)[0]; buf += strlen(buf); sprintf(buf, "+0x%08x", val); return 4; } size_t amd64_disassemble_sib(PIKE_OPCODE_T *pc, char *buf, const int *UNUSED(legacy_prefix), int modrm, int rex) { int sib = pc[0]; int bytes = 1; buf[0] = 0; if (((sib & 0x07) == 0x05) && !(rex & 1)) { switch (modrm & 0xc0) { case 0x00: /* Disp32 */ { INT32 val = ((INT32 *)(pc + 1))[0]; bytes += 4; if (val < 0) { sprintf(buf, "-0x%x", -val); } else { sprintf(buf, "0x%x", val); } } break; case 0x40: /* Disp8 + [EBP] */ { INT32 val = (pc + 1)[0]; bytes++; if (val < 0) { sprintf(buf, "-0x%x(%%rbp)", -val); } else { sprintf(buf, "0x%x(%%rbp)", val); } } break; case 0x80: /* Disp32 + [EBP] */ { INT32 val = ((INT32 *)(pc + 1))[0]; bytes += 4; if (val < 0) { sprintf(buf, "-0x%x(%%rbp)", -val); } else { sprintf(buf, "0x%x(%%rbp)", val); } } break; } } else { sprintf(buf, "%s", amd64_describe_reg(rex & 1, sib & 0x07)); } if ((sib & 0x38) != 0x20) { if (sib & 0xc0) { /* Scale factor active */ sprintf(buf + strlen(buf), "(%s*%d)", amd64_describe_reg(rex & 2, (sib>>3) & 0x07), 1<<((sib>>6) & 3)); } else { sprintf(buf + strlen(buf), "(%s)", amd64_describe_reg(rex & 2, (sib>>3) & 0x07)); } } return bytes; } size_t amd64_disassemble_modrm(PIKE_OPCODE_T *pc, char *buf, const int *legacy_prefix, int modrm, int rex) { size_t bytes = 0; int mod; char reg_buf[256]; if (legacy_prefix[3]) { /* Size prefix override. ==> 16 bits */ } reg_buf[0] = 0; buf[0] = 0; switch(modrm & 0xc0) { default: if ((modrm & 0xc7) == 0x05) { /* RIP + disp32 */ INT32 val = ((INT32 *)pc)[0]; if (val < 0) { sprintf(buf, "-0x%x(%%rip)", -val); } else { sprintf(buf, "0x%x(%%rip)", val); } return 4; } if ((modrm & 0x07) == 0x04) { bytes += amd64_disassemble_sib(pc + bytes, reg_buf, legacy_prefix, modrm, rex); } else { sprintf(reg_buf, "%s", amd64_describe_reg(rex & 1, modrm & 7)); } switch(modrm & 0xc0) { case 0x00: sprintf(buf, "%s", reg_buf); break; case 0x40: sprintf(buf, "%d(%s)", ((signed char *)pc)[bytes], reg_buf); bytes++; break; case 0x80: bytes += amd64_readint32(pc + bytes, buf); sprintf(buf + strlen(buf), "(%s)", reg_buf); break; } break; case 0xc0: sprintf(buf, "%s", amd64_describe_reg(rex & 1, modrm & 7)); break; } return bytes; } void amd64_disassemble_code(PIKE_OPCODE_T *pc, size_t len) { size_t pos; for (pos = 0; pos < len;) { size_t op_start = pos; size_t i; const char *opcode = NULL; const char *params[4] = { NULL, NULL, NULL, NULL, }; int legacy_prefix[4] = { 0, 0, 0, 0 }; int byte; int rex = 0; int modrm = 0; struct amd64_opcode *table = amd64_opcodes[0]; struct amd64_opcode *op; char buffers[4][256]; fprintf(stderr, "%p:\t", pc + pos); // Handle prefixes. while(1) { byte = pc[pos++]; op = table + byte; if (op->flags & OP_PREFIX) { legacy_prefix[op->flags & 3] = byte; continue; } break; } /* Handle REX */ if ((byte & 0xf0) == 0x40) { rex = byte; byte = pc[pos++]; op = table + byte; } while (op->flags & OP_MULTIBYTE) { table = amd64_opcodes[1 + op->flags & 0xff]; byte = pc[pos++]; op = table + byte; } opcode = op->name; if (op->flags & OP_RM) { modrm = pc[pos++]; params[0] = amd64_describe_reg(rex & 1, modrm & 0x07); if (op->flags & OP_OPS) { opcode = modrm_ops[op->flags & 0x0f][(modrm >> 3) & 0x07]; } else { params[0] = amd64_describe_reg(rex & 4, (modrm>>3) & 0x07); params[1] = buffers[1]; pos += amd64_disassemble_modrm(pc + pos, buffers[1], legacy_prefix, modrm, rex); } } if (op->flags & OP_REG) { int reg = byte & 0x07; params[0] = amd64_describe_reg(rex & 1, byte & 0x07); } if (op->flags & OP_IMM) { if (!params[1]) { params[1] = buffers[1]; buffers[1][0] = 0; } if (op->flags & (OP_8|OP_S8)) { sprintf(buffers[1] + strlen(buffers[1]), "$%+d", ((signed char *)pc)[pos++]); } else { sprintf(buffers[1] + strlen(buffers[1]), "$"); pos += amd64_readint32(pc + pos, buffers[1] + strlen(buffers[1])); } } else if (op->flags & OP_PCREL) { INT32 val; if (!params[1]) { params[1] = buffers[1]; buffers[1][0] = 0; } if (op->flags & (OP_8|OP_S8)) { val = ((signed char *)pc)[pos++]; } else { val = ((INT32 *)(pc + pos))[0]; pos += 4; } sprintf(buffers[1] + strlen(buffers[1]), "%p", pc + (pos + val)); } if (op->flags & OP_B_RM) { /* Swap the two parameters. */ const char *tmp = params[0]; params[0] = params[1]; params[1] = tmp; } if (opcode) { fprintf(stderr, "%s", opcode); if (params[0]) { fprintf(stderr, " %s", params[0]); if (params[1]) { fprintf(stderr, ","); } } if (params[1]) { fprintf(stderr, " %s", params[1]); } } else { fprintf(stderr, ".byte 0x%02x", byte); } for(i = 0; (op_start + i) < pos; i++) { if (!(i & 7)) { fprintf(stderr, "\n\t#"); } fprintf(stderr, " %02x", pc[op_start + i]); } fprintf(stderr, "\n"); } }

pike.git/ src/ code/ amd64.c > 2ad55eb2ff181db012b7e5e2d62cc87f991bdf9e [Annotate]