pike.git / src / code / amd64.c

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pike.git/src/code/amd64.c:578:   static void add_mem32_imm( enum amd64_reg reg, int offset, int imm32 )   {    low_add_mem_imm( 0, reg, offset, imm32 );   }      static void add_mem_imm( enum amd64_reg reg, int offset, int imm32 )   {    low_add_mem_imm( 1, reg, offset, imm32 );   }    + #ifndef USE_VALGRIND   static void add_mem8_imm( enum amd64_reg reg, int offset, int imm32 )   {    int r2 = imm32 == -1 ? 1 : 0;    if( !imm32 ) return;    rex( 0, 0, 0, reg );       if( imm32 == 1 || imm32 == -1 )    opcode( 0xfe ); /* INCL r/m8 */    else if( imm32 >= -128 && imm32 < 128 )    opcode( 0x80 ); /* ADD imm8,r/m32 */    else    Pike_fatal("Not sensible");       offset_modrm_sib( offset, r2, reg );    if( imm32 != 1 && !r2 )    {    ib( imm32 );    }   } -  + #endif      static void sub_reg_imm( enum amd64_reg reg, int imm32 )   {    if( !imm32 ) return;       if( imm32 < 0 )    /* This makes the disassembly easier to read. */    return add_reg_imm( reg, -imm32 );       rex( 1, 0, 0, reg );
pike.git/src/code/amd64.c:976:   {    /* Push all registers that the ABI requires to be preserved. */    push(P_REG_RBP);    mov_reg_reg(P_REG_RSP, P_REG_RBP);    push(P_REG_R15);    push(P_REG_R14);    push(P_REG_R13);    push(P_REG_R12);    push(P_REG_RBX);    sub_reg_imm(P_REG_RSP, 8); /* Align on 16 bytes. */ - #ifdef USE_VALGRIND -  mov_imm_mem32(0, P_REG_RSP, 0 ); /* clear counter used by check_threads_etc */ - #endif +     mov_reg_reg(ARG1_REG, Pike_interpreter_reg);    amd64_flush_code_generator_state();   }      void amd64_flush_code_generator_state(void)   {    sp_reg = -1;    fp_reg = -1;    ret_for_func = 0;    mark_sp_reg = -1;
pike.git/src/code/amd64.c:1479:    add_mem_imm( P_REG_RAX, 0, 0x80 );    }    mov_imm_reg( (ptrdiff_t)branch_check_threads_etc, P_REG_RAX );    jmp_reg(P_REG_RAX); /* ret in BCTE will return to desired point. */    amd64_align();    }    if( !code_only )    {    LABEL_A;    /* Use C-stack for counter. We have padding added in entry */ + #ifndef USE_VALGRIND    add_mem8_imm( P_REG_RSP, 0, 1 );    jno( &label_B ); -  + #endif    call_rel_imm32( branch_check_threads_update_etc ); -  + #ifndef USE_VALGRIND    LABEL_B; -  + #endif    }   }         void amd64_init_interpreter_state(void)   {    instrs[F_CATCH - F_OFFSET].address = inter_return_opcode_F_CATCH;   }      static void amd64_return_from_function()