pike.git / src / code / amd64.c

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pike.git/src/code/amd64.c:4464:   {    return read_pointer(offset) + offset + 4;   }      #define OP_PREFIX 0x10000000UL   #define G1 (OP_PREFIX|0)   #define G2 (OP_PREFIX|1)   #define G3 (OP_PREFIX|2)   #define G4 (OP_PREFIX|3)    + /* Table switch */ + #define OP_MULTIBYTE 0x20000000UL + #define OP_F (OP_MULTIBYTE|0) + #define OP_F_38 (OP_MULTIBYTE|1) + #define OP_F_3A (OP_MULTIBYTE|2) +    /* Additional fields */   #define OP_RM 0x00010000 /* ModR/M */   #define OP_DISPL 0x00020000 /* Displacement */   #define OP_IMM 0x00040000 /* Immediate */      #define OP_PCREL 0x00080000 /* PC-relative */      /* Implicit arguments */   #define OP_REG 0x00100000 /* Register in low 3 bits. */   #define OP_IMPLICIT_A 0x00200000
pike.git/src/code/amd64.c:4488:      #define OP_B_RM 0x00008000 /* B arg before RM arg. */      /* Operand widths */   #define OP_8 0x01000000 /* 8-bit */   #define OP_S8 0x02000000 /* 8-bit sign extended to 16 */      /* ModRM lookup */   #define OP_OPS 0x10000000 /* Lookup in modrm_ops */    - /* Table switch */ - #define OP_F 0x20000000 /* Switch to table amd64_opcodes_F */ +       #define OP_S 0      #define REG (OP_REG)         #define RRM8 (OP_8|OP_RM|OP_B_RM)   #define RMR8 (OP_8|OP_RM)   #define RMR (OP_RM)   #define RRM (OP_RM|OP_B_RM)
pike.git/src/code/amd64.c:4556:    "test", NULL, NULL, NULL,    NULL, NULL, NULL, NULL,    },   };      struct amd64_opcode {    const char *name;    unsigned INT64 flags;   };    - static struct amd64_opcode amd64_opcodes[256] = { + static struct amd64_opcode amd64_opcodes[3][256] = { +  /* Main table. */ + {    /* 0x00 */    { "add", RMR8, }, { "add", RMR, }, { "add", RRM8, }, { "add", RRM, },    { "add", ALI8, }, { "add", AI, }, { NULL, 0, }, { NULL, 0, },    { "or", RMR8, }, { "or", RMR, }, { "or", RRM8, }, { "or", RRM, }, -  { "or", ALI8, }, { "or", AI, }, { NULL, 0, }, { "", OP_F, }, +  { "or", ALI8, }, { "or", AI, }, { NULL, 0, }, { "F", OP_F, },       /* 0x10 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },       /* 0x20 */    { "and", RMR8, }, { "and", RMR, }, { "and", RRM8, }, { "and", RRM, },    { "and", ALI8, }, { "and", AI, }, { "es", G2, }, { NULL, 0, },
pike.git/src/code/amd64.c:4652:    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "jcxz", PCREL8, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { "call", PCREL, }, { NULL, 0, }, { NULL, 0, }, { "jmp", PCREL8, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },       /* 0xf0 */    { "lock", G1, }, { NULL, 0, }, { "repne", G1, }, { "rep", G1, },    { NULL, 0, }, { "cmc", 0, }, { "neg", RM8OP|2, }, { "neg", RMOP|2, },    { "clc", 0, }, { NULL, 0, }, { "cli", 0, }, { NULL, 0, },    { "cld", 0, }, { NULL, 0, }, { "dec", RM8OP|3, }, { "dec", RMOP|3, }, - }; -  - static struct amd64_opcode amd64_opcodes_F[256] = { + }, + /* Opcode prefix 0x0f. */ + {    /* 0x00 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },       /* 0x10 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },
pike.git/src/code/amd64.c:4676:       /* 0x20 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },       /* 0x30 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { "aes|blendvps/d|crc32", OP_F_38, }, { NULL, 0, }, { "aes|blendps/d", OP_F_3A, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, -  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +        /* 0x40 */    { "cmovo", RRM, }, { "cmovno", RRM, }, { "cmovb", RRM, }, { "cmovae", RRM, },    { "cmove", RRM, }, { "cmovne", RRM, }, { "cmovbe", RRM, }, { "cmova", RRM, },    { "cmovs", RRM, }, { "cmovns", RRM, }, { "cmovp", RRM, }, { "cmovnp", RRM, },    { "cmovel", RRM, }, { "cmovge", RRM, }, { "cmovle", RRM, }, { "cmovg", RRM, },       /* 0x50 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },
pike.git/src/code/amd64.c:4716:    { "js", PCREL, }, { "jns", PCREL, }, { "jp", PCREL, }, { "jnp", PCREL, },    { "jl", PCREL, }, { "jge", PCREL, }, { "jle", PCREL, }, { "jg", PCREL, },       /* 0x90 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { "eq", RM, }, { "neq", RM, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { "lt", RM, }, { "gte", RM, }, { "lte", RM, }, { "gt", RM, },       /* 0xa0 */ -  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "bt", RMR, }, +  { NULL, 0, }, { NULL, 0, }, { "cpuid", 0, }, { "bt", RMR, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, -  +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "bts", RMR, }, +  { NULL, 0, }, { NULL, 0, }, { "clflush", RM, }, { "imul", RRM, }, +  +  /* 0xb0 */ +  { "cmpxchg", RMR8, }, { "cmpxchg", RMR, }, { NULL, 0, }, { "btr", RMR, }, +  { NULL, 0, }, { NULL, 0, }, { "movzx", RRM, }, { "movzx", RRM, }, +  { "bsf", RRM, }, { "bsr", RRM, }, { "bt", RIOP|5, }, { "btc", RMR, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, -  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "imul", RRM, }, +     -  +  /* 0xc0 */ +  { NULL, 0, }, { NULL, 0, }, { "cmpp/ss/d", RRMI8, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "cmpxchg8b", RM, }, +  { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, +  { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, { "bswap", REG, }, +  +  /* 0xd0 */ +  { "addsubps/d", RRM, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0xe0 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0xf0 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, + }, + /* Opcode prefix 0x0f 0x38: AES, BLENDVP, CRC32. */ + { +  /* 0x00 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x10 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { "blendvps", RRM, }, { "blendvpd", RRM, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x20 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x30 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x40 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x50 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x60 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x70 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x80 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x90 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0xa0 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +     /* 0xb0 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, -  { NULL, 0, }, { NULL, 0, }, { "movzx", RRM, }, { "movzx", RRM, }, -  { NULL, 0, }, { NULL, 0, }, { "bt", RI, }, { NULL, 0, }, +     { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, -  +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },       /* 0xc0 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },       /* 0xd0 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, -  +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "aesimc", RRM, }, +  { "aesenc", RRM, }, { "aesenclast", RRM, }, { "aesdec", RRM, }, { "aesdeclast", RRM, }, +  +  /* 0xe0 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, -  +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    -  +  /* 0xf0 */ +  { "crc32", RRM8, }, { "crc32", RRM, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, + }, + /* Opcode prefix 0x0f 0x3a: AES, BLENDP. */ + { +  /* 0x00 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { "blendps", RRMI8, }, { "blendpd", RRMI8, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x10 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x20 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x30 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x40 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x50 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x60 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x70 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x80 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0x90 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0xa0 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0xb0 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0xc0 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  +  /* 0xd0 */ +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, +  { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { "aeskeygenassist", RRMI8, }, +     /* 0xe0 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },       /* 0xf0 */    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, },    { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, { NULL, 0, }, -  + },   };      const char *amd64_registers[16] = {    "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",    "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",   };      const char *amd64_describe_reg(int rex, int reg)   {    if (rex) reg += 8;
pike.git/src/code/amd64.c:4900:    size_t pos;    for (pos = 0; pos < len;) {    size_t op_start = pos;    size_t i;    const char *opcode = NULL;    const char *params[4] = { NULL, NULL, NULL, NULL, };    int legacy_prefix[4] = { 0, 0, 0, 0 };    int byte;    int rex = 0;    int modrm = 0; -  struct amd64_opcode *table = amd64_opcodes; +  struct amd64_opcode *table = amd64_opcodes[0];    struct amd64_opcode *op;    char buffers[4][256];       fprintf(stderr, "%p:\t", pc + pos);       // Handle prefixes.    while(1) {    byte = pc[pos++];    op = table + byte;    if (op->flags & OP_PREFIX) {
pike.git/src/code/amd64.c:4924:    break;    }       /* Handle REX */    if ((byte & 0xf0) == 0x40) {    rex = byte;    byte = pc[pos++];    op = table + byte;    }    -  if (byte == 0x0f) { -  table = amd64_opcodes_F; +  while (op->flags & OP_MULTIBYTE) { +  table = amd64_opcodes[1 + op->flags & 0xff];    byte = pc[pos++];    op = table + byte;    }       opcode = op->name;       if (op->flags & OP_RM) {    modrm = pc[pos++];    params[0] = amd64_describe_reg(rex & 1, modrm & 0x07);    if (op->flags & OP_OPS) {